TAS3004PFB Datasheet, PDF (19/84 Pages) Texas Instruments – Digital Auido Processor With Codec

2.3.2 I²S Serial Interface Format—Monaural ADC Mode, B Left Input Selected
The monaural output mode for the I²S serial interface format is for 16, 18, 20, and 24 bits with the following bits in
the analog control register set as shown:
• Bit 7 (ADM) is set to 1.
• Bit 6 (LRB) is cleared to 0.
• Bit 1 (INP) is set to 1.
Figure 2–5 shows the following characteristics of this protocol:
• Left channel is transmitted when LRCLK is either high or low.
• SDIN is sampled with the rising edge of SCLK.
• SDOUT is transmitted on the falling edge of SCLK.
• If LRCLK phase changes by more than 10MCLK, the codec automatically resets.
SCLK
LRCLK = fS
… … … … … … ^{SDIN X MSB}
LSB
X MSB
LSB
… … … … … … ^{SDOUT0 X MSB}
LSB
X MSB
LSB
Left Channel
Left Channel
Figure 2–5. I²S Serial Interface Format—Monaural ADC Mode, B Left Input Selected
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