DAC5670-SP Datasheet, PDF (19/30 Pages) Texas Instruments – 14-BIT 2.4-GSPS DIGITAL-TO-ANALOG CONVERTER

DAC5670-SP
www.ti.com
SGLS386A – JANUARY 2009 – REVISED DECEMBER 2009
Figure 13 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5670, valid for the
following pins: RESTART, LVDS_HTB, INV_CLK, SLEEP, NORMAL, A_ONLY, A_ONLY_INV, and A_ONLY_ZS.
Figure 13.
The DAC5670 is clocked at the DAC sample rate. Each input port runs at a maximum of 1.2 GSPS. The
DAC5670 provides an output clock at one-half the input port data rate (DACCLK/4), monitors an additional
reference bit input sequence, and adjusts the output clock delay to optimize the data latch relative to the
reference bit with a DLL. The DLL delay automatically adjusts for drift over temperature and time.
Data Source
DAC5670
DA_P[13:0]
DA_N[13:0]
DB_P[13:0]
Input
Registers
DB_N[13:0]
DTCLK_P
DTCLK_N
DLYCLK_P
Delay
Locked
Loop
(DLL)
÷2
÷2
DLYCLK_N
DACCLK_P
DACCLK_N
Figure 14. DLL Input Loop Simplified Block Diagram
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC5670-SP
Submit Documentation Feedback
19