BQ76PL536 Datasheet, PDF (19/58 Pages) Texas Instruments – 3 to 6 Series Cell Lithium-Ion Battery Monitor and Secondary Protection IC for EV and HEV Applications

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Write ADC_CONFIG[ADC_ON] = 1 (0x30 = 01xx xxxxb)
Note: To convert all inputs typically, use 0x30 = 0111 1101b
bq76PL536
SLUSA08A – DECEMBER 2009 – REVISED JULY 2010
9.8.2.1.2 Alternate Method - Use Shadow RAM Feature (EPROM 0x40 Programmed Value is Don’t Care):
The shadow RAM feature allows temporarily overwriting EPROM contents. At RESET, group-3 RAM registers
are loaded from OTP EPROM. The device always uses the contents of the RAM register internally to control the
device. The RAM register may be subsequently overwritten with a new value to modify the device defaults
programmed in EPROM. The new value is valid until the next device RESET. This example assumes that all
inputs are converted.
1. Setup for 6-µs/ch conversion time:
Write SHDW_CTRL[] = 0x35 (register 0x3a = 0x35) to enable the write to FUNCTION_CONFIG[].
Immediately followed by:
Write FUNCTION_CONFIG[] = 0x50 (register 0x40 = 0x50)
2. Prior to any conversion:
Write ADC_CTRL[] = 0x7d (register 0x30 = 0x7d)
Wait >1 ms before converting after setting ADC_ON = 1 in the previous step.
3. Converting:
Conversions are now initiated normally, using the CONV_H pin or the CONVERT[CONV] register bit.
Note: Power may be significantly reduced by setting the bit ADC_ON = 0.
Secondary Protection
The bq76PL536 integrates dedicated overvoltage and undervoltage fault detection for each cell and two
overtemperature fault detection inputs for each device. The protection circuits use a separate band-gap reference
from the ADC system and operate independently. The protector also uses separate I/O pins from the main
communications bus, and therefore is capable of signaling faults in hardware without intervention from the Host
CPU.
Protector Functionality
When a fault state is detected, the respective fault flag in the FAULT_STATUS[] or ALERT_STATUS[] registers
is set. All flags in the FAULT and ALERT registers are then ORed into the DEVICE_STATUS[] FAULT and
ALERT bits. The FAULT and ALERT bits in DEVICE_STATUS[] in turn cause the hardware FAULT_S or
ALERT_S pin to be set. The bits in DEVICE_STATUS[] and the hardware pins are latched until reset by the host
via SPI command, ensuring that the host CPU does not miss an event.
A separate timer is provided for each fault source (cell overvoltage, cell undervoltage, overtemperature) to
prevent false alarms. Each timer is programmable from 100 µs to more than 3 s. The timers may also be
disabled, which causes fault conditions to be sensed immediately and not latched.
The clearing of the FAULT or ALERT flag (and pin) occurs when the respective flag is written to a 1, which also
restarts the respective fault timer. This also clears the FAULT_S (_H) or ALERT_S (_H) pin. If the actual fault
remains present, the FAULT (ALERT) pin is again asserted at the expiration of the timer. This cycle repeats until
the cause of the fault is removed.
On exit from the SLEEP state, the COV, CUV, and OT fault comparators are disabled for approximately 200 µs
to allow internal circuitry to stabilize and prevent false error condition detection.
Using the Protector Functions With 3-5 Cells
The OV/UV condition can be ignored for unused channels by setting the FUNCTION_CONFIG[CNx] bits to the
maximum number of cells connected to the device. If fewer than 6 cells are configured, the corresponding OV/UV
faults are ignored. For example, if the FUNCTION_CONFIG[] bits are set to xxxx 1000, then the OV/UV
comparators are disabled for cells 5 and 6. Correct setting of this register prevents spurious false alarms.
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