AFE5803 Datasheet, PDF (19/52 Pages) Texas Instruments – Fully Integrated, 8-Channel Ultrasound Analog Front End

AFE5803
www.ti.com
SLOS763A – JANUARY 2012 – REVISED JANUARY 2012
TIMING CHARACTERISTICS⁽¹⁾
Typical values are at 25°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, Differential clock, C_LOAD =
5pF, R_LOAD = 100 Ω, 14Bit, sample rate = 65MSPS, unless otherwise noted. Minimum and maximum values are across the
full temperature range T_MIN = 0°C to T_MAX = 85°C with AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
ta
Aperture delay
The delay in time between the rising edge of the input sampling
clock and the actual time at which the sampling occurs
0.7
3
ns
Aperture delay
matching
Across channels within the same device
±150
ps
t_j
Aperture jitter
ADC latency
Default, after reset, or / 0 x 2 [12] = 1, LOW_LATENCY = 1
450
Fs rms
Input
11/8
clock
cycles
t_delay
Data and frame clock Input clock rising edge (zero cross) to frame clock rising edge (zero
delay
cross) minus 3/7 of the input clock period (T).
3 5.4
7 ns
Δt_delay
Delay variation
At fixed supply and 20°C T difference. Device to device
–1
1 ns
t_RISE
Data rise time Data fall ^{Rise time measured from –100 mV to 100 mV Fall time measured}
0.14
ns
t_FALL
time
from 100 mV to –100 mV 10 MHz < f_CLKIN < 65 MHz
0.15
t_FCLKRISE
t_FCLKFALL
Frame clock rise time Rise time measured from –100mV to 100mV Fall time measured
Frame clock fall time from 100 mV to –100 mV 10 MHz < f_CLKIN < 65MHz
0.14
ns
0.15
Frame clock duty cycle Zero crossing of the rising edge to zero crossing of the falling edge 48% 50% 52%
t_DCLKRISE
t_DCLKFALL
Bit clock rise time Bit
clock fall time
Rise time measured from –100mV to 100mV Fall time measured
from 100 mV to –100 mV 10 MHz < f_CLKIN < 65MHz
0.13
ns
0.12
Bit clock duty cycle
Zero crossing of the rising edge to zero crossing of the falling edge
10 MHz < f_CLKIN < 65 MHz
46%
54%
(1) Timing parameters are ensured by design and characterization; not production tested.
OUTPUT INTERFACE TIMING^(1)(2)(3)
f_CLKIN,
Input Clock
Frequency
Setup Time (t_su), ns
(for output data and frame clock)
Data Valid to Input Clock
Zero-Crossing
MHz
MIN
TYP
MAX
65/14bit
0.24
0.37
50/14bit
0.41
0.54
40/14bit
0.55
0.70
30/14bit
0.87
1.10
20/14bit
1.30
1.56
Hold Time (t_h), ns
(for output data and frame clock)
Input Clock Zero-Crossing to Data
Invalid
MIN
TYP
MAX
0.24
0.38
0.46
0.57
0.61
0.73
0.94
1.1
1.46
1.6
t_PROG = (3/7)x T + t_delay, ns
Input Clock Zero-Cross (rising edge)
to Frame Clock Zero-Cross (rising
edge)
MIN
TYP
MAX
11
12
12.5
13
13.9
14.4
15
16
16.7
18.5
19.5
20.1
25.7
26.7
27.3
(1) FCLK timing is the same as for the output data lines. It has the same relation to DCLK as the data pins. Setup and hold are the same
for the data and the frame clock.
(2) Data valid is logic HIGH = +100mV and logic LOW = -100mV
(3) Timing parameters are ensured by design and characterization; not production tested.
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): AFE5803
Submit Documentation Feedback
19