ADS8508 Datasheet, PDF (19/27 Pages) Texas Instruments – 12-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER

ADS8508
www.ti.com
SLAS433 – SEPTEMBER 2005
The external reference voltage can vary from 2.3 V to 2.7 V. The reference voltage determines the size of the
least significant bit (LSB). The larger reference voltages produce a larger LSB, which can improve SNR. Smaller
reference voltages can degrade SNR.
2.2 mF
+15V
22 pF
GND
Vin
100 nF
1 kW
22 pF
Pin 7 Pin 1
Pin 2
−
OPA 627
+
Pin3
Pin 4
1 kW
10 pF
Pin5
GND
Pin 6
GND
2.2 mF
100 nF
−15 V
GND
200 W
100 W
GND
33.2 kW
2.2 mF
ADS8508
R1_IN
AGND
R2_IN
R3_IN
CAP
AGND2
2.2 mF
GND
Figure 27. Typical Driving Circuitry (±10 V, No Trim)
Table 3. Input Range Connections (see Figure 28 and Figure 29 for complete
information)
ANALOG
INPUT RANGE
±10 V
±5 V
±3.33 V
0 V to 10 V
0 V to 5 V
0 V to 4 V
CONNECT R1_IN VIA
200 Ω TO
V_IN
AGND
V_IN
AGND
AGND
V_IN
CONNECT R2_IN VIA
100 Ω TO
AGND
V_IN
V_IN
V_IN
AGND
AGND
CONNECT
R3 TO
CAP
CAP
CAP
AGND
V_IN
V_IN
IMPEDANCE
11.5 kΩ
6.7 kΩ
5.4 kΩ
6.7 kΩ
5.0 kΩ
5.4 kΩ
SPECIFIC FUNCTION
Initiate conversion and out-
put data using internal clock
CS
1>0
0
R/C
0
1>0
BUSY
1
1
Initiate conversion and out- 1 > 0 0
1
put data using external clock _{0 1 > 0}
1
1>0 1
1
Incorrect conversions
Power down
1>0 1
0 0>1
0
0
0
0
0>1
x
x
x
x
x
x
Table 4. Control Truth Table
EXT/INT
0
0
1
1
1
1
1
x
x
x
DATACLK
Output
Output
Input
Input
Input
Input
Input
x
x
x
PWRD
0
0
0
0
x
0
0
0
0
1
SB/BTC
x
x
x
x
x
x
x
x
x
x
OPERATION
Initiates conversion n. Data from conversion n - 1
clocked out on DATA synchronized to 16 clock
pulses output on DATACLK.
Initiates conversion n.
Initiates conversion n.
Outputs a pulse on SYNC followed by data from
conversion n clocked out synchronized to external
DATACLK.
Outputs a pulse on SYNC followed by data from
conversion n - 1 clocked out synchronized to
external DATACLK.⁽¹⁾ Conversion n in process.
CS or R/C must be HIGH or a new conversion will
be initiated without time for acquisition.
Analog circuitry powered. Conversion can pro-
ceed..
Analog circuitry disabled. Data from previous
conversion maintained in output registers.
(1) See Figure XXX for the constraints on previous data valid during a conversion.
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