ADS5463_07 Datasheet, PDF (19/27 Pages) Texas Instruments – 12-Bit, 500-MSPS Analog-to-Digital Converter

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Application Information (continued)
ADS5463
SLAS515 – NOVEMBER 2006
1000 pF
VIN
THS9001
1000 pF
18 mH
VIN
THS9001
1000 pF
1000 pF
AIN
39 pF
50 W
50 W _{0.1 mF}
AIN
ADS5463
Figure 37. Using the THS9001 IF Amplifier With the ADS5463
S0177-03
From ^VIN
50 W
Source
49.9 W
100 W
78.9 W
0.22 mF
100 W
78.9 W
348 W
+5V
THS4509
CM
49.9 W
49.9 W ^{18 pF}
AIN
ADS5463
AIN VREF
49.9 W
0.22 mF
0.22 mF
348 W
0.1 mF
0.1 mF
Figure 38. Using the THS4509 With the ADS5463
S0193-02
For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like
the THS4509 (see Figure 38) is a good solution, as it minimizes board space and reduces the number of
components.
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5463. The 50-Ω resistors and 18-pF
capacitor between the THS4509 outputs and ADS5463 inputs (along with the input capacitance of the ADC) limit
the bandwidth of the signal to about 70 MHz (–3 dB). Input termination is accomplished via the 78.9-Ω resistor
and 0.22-µF capacitor to ground, in conjunction with the input impedance of the amplifier circuit. A 0.22-µF
capacitor and 49.9-Ω resistor are inserted to ground across the 78.9-Ω resistor and 0.22-µF capacitor on the
alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω
feedback resistor. See the THS4509 data sheet for further component values to set proper 50-Ω termination for
other common gains. Because the ADS5463 recommended input common-mode voltage is 2.4 V, the THS4509
is operated from a single power supply input with V S+ = 5 V and V S– = 0 V (ground). This maintains maximum
headroom on the internal transistors of the THS4509.
Clock Inputs
The ADS5463 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low-input-frequency applications, where
jitter may not be a big concern, the use of a single-ended clock (see Figure 39) could save some cost and board
space without any trade-off in performance. When clocked with this configuration, it is best to connect CLK to
ground with a 0.01-µF capacitor, while CLK is ac-coupled with a 0.01-µF capacitor to the clock source, as shown
in Figure 39.
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