LM3S8733 Datasheet, PDF (182/616 Pages) Texas Instruments – Stellaris® LM3S8733 Microcontroller

General-Purpose Input/Outputs (GPIOs)
9.1.2
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 9-2 on page 182, where u is data unchanged by the write.
Figure 9-2. GPIODATA Write Example
ADDR[9:2] 9 8 7 6 5 4 3 2 1 0
0x098 0 0 1 0 0 1 1 0 0 0
0xEB 1 1 1 0 1 0 1 1
GPIODATA u u 1 u u 0 1 u
76543210
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-3 on page 182.
Figure 9-3. GPIODATA Read Example
ADDR[9:2] 9 8 7 6 5 4 3 2 1 0
0x0C4 0 0 1 1 0 0 0 1 0 0
GPIODATA 1 0 1 1 1 1 1 0
Returned Value 0 0 1 1 0 0 0 0
76543210
Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 190)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 191)
■ GPIO Interrupt Event (GPIOIEV) register (see page 192)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 193).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 194 and page 195). As the name implies, the GPIOMIS register only shows interrupt
182
June 22, 2010
Texas Instruments-Production Data