TRF6900 Datasheet, PDF (18/34 Pages) Texas Instruments – SINGLE-CHIP RF TRANSCEIVER

TRF6900
SINGLE-CHIP RF TRANSCEIVER
SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000
TRF6900 direct digital synthesizer implementation (continued)
The frequency of the reference oscillator, ƒ_ref, is the DDS sample frequency, which also determines the
maximum DDS output frequency. Together with the accumulator width (in bits), the frequency resolution of the
DDS can be calculated. Multiplied by the divider ratio (prescaler) of the PLL, N, the minimum frequency step
size of the TRF6900 is calculated as follows:
+ Dƒ
N
ƒ_ref
2²⁴
The 24-bit accumulator can be programmed via two 22-bit frequency setting registers (the A-word determines
the mode0 frequency, the B-word determines the mode1 frequency) with the two MSB bits set to zero.
Consequently, the maximum bit weight of the DDS system is reduced to 1/8 (see Figure 17). This bit weight
corresponds to a VCO output frequency of (ƒ_ref/8) × N. Depending on the MODE terminal’s (terminal 17) logic
level, the internal mode select logic loads the frequency register with either the DDS_0 or DDS_1 frequency
(see Figure 16 and Figure 17).
22
DDS Frequency Setting For Mode0/1
From A-Word/B-Word
0 0 X X ....
MSB
23 22 21 20 . . .
Bit weight: 1/2 1/4 1/8 1/16 . . .
FSK Frequency Deviation Register – DEV
. . . X X X X X ^{DDS Frequency Register}
LSB
... 4 3 2 1 0
... 1
8
2 ²⁴
0 0 ^....
MSB
23 22 ^{. . . .}
.... _{X X X X X X X X 0 0}
LSB
...._{9 8 7 6 5 4 3 2 1 0}
DDS Frequency Register
Figure 17. Implementation of the DDS Frequency and FSK Frequency
Deviation in the DDS Frequency Register
The VCO output frequency, ƒ_out, which is dependent on the DDS_x frequency settings ( DDS_0 in the A-word
or DDS_1 in the B-word ), can be calculated as follows:
+ + ƒ_out
DDS_x
N
ƒ_ref
2²⁴
N
ƒ_ref DDS_x
2²⁴
If FSK modulation is selected (MM=0; C-Word, bit 16) the 8-bit FSK deviation register can be used to program
the frequency deviation of the 2-FSK modulation. Figure 17 illustrates where the 8 bits of the FSK deviation
register map into the 24-bit DDS frequency register. Since the two LSBs are set to zero, the total FSK deviation
can be determined as follows:
+ Dƒ_2–FSK
N
DEV ƒ_ref
2²²
Hence, the 2-FSK frequency, set by the level of TX_DATA, is calculated as follows:
+ ^{+ ƒ}out1:TX_DATA Low
N
ƒ_ref DDS_x
2²⁴
+ ^{+ ƒ}out2:TX_DATA High ^N
ƒ_ref
) (DDS_x 4
2²⁴
DEV)
This frequency modulated output signal is used as a reference input signal for the PLL circuit.
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