TPS65148 Datasheet, PDF (18/30 Pages) Texas Instruments – Compact TFT LCD Bias IC for Monitor with VCOM Buffer, Voltage Regulator for Gamma Buffer and Reset Function

TPS65148
SLVS904 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
GATE VOLTAGE SHAPING FUNCTION
External Positive
Charge Pump
V_IN
V_S
SW SW
SUP
Power Transistor
Boost Converter
VGH
VFLK
VDPM
M1
Gate Voltage
Shaping
(GVS)
M2
VGHM
RE
PGND
AGND
Figure 22. Gate Voltage Shaping Block Diagram
The Gate Voltage Shaping is controlled by the flicker input signal VFLK, except during start-up where it is kept at
low state, whatever the VFLK signal is. The VGHM output is enabled once VDPM voltage is higher than V_ref =
1.240 V. The capacitor connected to VDPM (C13 on Figure 27) pin sets the delay from the boost converter
Power Good (90% of its nominal value).
C_VDPM =
I_DPM ´ t_DPM
V_ref
=
20 mA ´ t_DPM
1.240 V
(7)
VFLK = 'high' → V_GHM = V_GH
VFLK = 'low' → V_GHM discharges through Re resistor
The slope at which V_GHM discharges is set by the external resistor connected to RE, the internal MOSFET
R_DS(ON) (typically 13Ω for M2 – see Figure 22) and by the external gate line capacitance connected to VGHM pin.
VFLK
Boost
Power Good
VFLK = “high”
Unknown state
Delay set by
VDPM
VFLK = “low”
VGH
VGHM
Slope set by
Re
0V
Figure 23. Gate Voltage Shaping Timing
18
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