TPS55330_15 Datasheet, PDF (18/32 Pages) Texas Instruments – TPS55330 Integrated 5-A, 24-V Boost/SEPIC/Flyback DC-DC Regulator

TPS55330
SLVSBX8A – MAY 2013 – REVISED DECEMBER 2014
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In this conservative design example, the diode is chosen to be rated for the maximum output current of 3.6 A.
During normal operation with 2.1 mA output current and assuming a Schottky diode drop of 0.5 V, the diode must
be capable of dissipating 1 W. The recommended minimum ratings for this design are a 20 V, 4 A diode.
However to improve the flexibility of this design, a Diodes Inc B520-13-F in an SMC package is used with voltage
and current ratings of 20 V and 5 A.
8.2.2.10 Compensating the Control Loop (R3, C4, C5)
The TPS55330 requires external compensation which allows the loop response to be optimized for each
application. The COMP pin is the output of the internal error amplifier. An external resistor R3 and ceramic
capacitor C4 are connected to the COMP pin to provide a pole and a zero, shown in the application circuit. This
pole and zero, along with the inherent pole and zero of a boost converter, determine the closed loop frequency
response. This is important for converter stability and transient response. Loop compensation should be
designed for the minimum operating voltage.
The following equations summarize the loop equations for the TPS55330 configured as a CCM boost converter.
They include the power stage output pole (ƒ_OUT) and the right-half-plane zero (ƒ_RHPZ) of a boost converter
calculated with Equation 27 and Equation 28 respectively. When calculating ƒ_OUT it is important to include the
derating of ceramic output capacitors. In the example with an estimated 61 µF capacitance, these frequencies
are calculated to 521 kHz and 2.2 kHz respectively. The DC gain (A) of the power stage is calculated with
Equation 27 and is 39.9 dB in this design. The compensation pole (ƒ_P) and zero (ƒ_Z) generated by R3, C4 and
internal transconductance amplifier are calculated with Equation 30 and Equation 31, respectively.
Most CCM boost converters will have a stable control loop if f_Z is set slightly above ƒ_P through proper sizing of
R3 and C4. A good starting point is C4 = 0.1 µF and R3 = 2kΩ. Increasing R3 or reducing C4 increases the
closed loop bandwidth, and therefore improves the transient response. Adjusting R3 and C4 in opposite direction
increases the phase and gain margin of the loop, which improves loop stability. It is generally recommended to
limit the bandwidth of the loop to the lower of either 1/5 of the switching frequency ƒ_SW or 1/3 the RHPZ
frequency, ƒ_RHPZ shown in Equation 28. The spreadsheet tool located in the TPS55330 product folder at
SLVC430 can also be used to aid in compensation design.
2
¦_OUT » _{2p ´ ROUT ´ COUT}
(27)
¦_RHPZ
»
R_OUT
2p ´ L
´
æ
ç
è
V_IN
V_OUT
ö²
÷
ø
(28)
A
=
1.229
V_OUT
´ Gea ´10MW ´
V_OUT
V_IN
´ R_SENSE
´ R_OUT
´
1
2
(29)
1
¦_P = _{2p ´10MW ´ C4}
(30)
1
¦_Z = _{2p ´ R3 ´ C4}
(31)
¦co1 = ^¦SW
5
(32)
¦co2 = ^¦RHPZ
3
(33)
Where
• C_OUT is the equivalent output capacitor (C_OUT=C8+C9+C10)
• R_OUT is the equivalent load resistance (V_OUT/I_OUT)
• Gea is the error amplifier transconductance located in the Electrical Characteristics table
• R_SENSE (15 mΩ, typical) is the sense resistor in the current control loop
• ƒ_co1 and ƒ_co2 are possible bandwidth.
18
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