TLV320AIC3254_15 Datasheet, PDF (18/53 Pages) Texas Instruments – TLV320AIC3254 Ultra Low Power Stereo Audio Codec with Embedded miniDSP

TLV320AIC3254
SLAS549D – SEPTEMBER 2008 – REVISED NOVEMBER 2014
8.14 DSP Timing in Master Mode (see Figure 3)
t_d(WS)
t_d(DO-BCLK)
t_s(DI)
t_h(DI)
t_r
t_f
WCLK delay
BCLK to DOUT delay
DIN setup
DIN hold
Rise time
Fall time
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IOVDD = 1.8V
MIN
MAX
30
22
8
8
24
24
IOVDD = 3.3V
MIN MAX
20
20
8
8
12
12
UNIT
ns
ns
ns
ns
ns
ns
WCLK
t_d(WS)
t_d(WS)
BCLK
DOUT
DIN
t_d(DO-BCLK)
t_s(DI)
All specifications at 25°C, DVdd = 1.8V
Figure 3. DSP Timing in Master Mode
t_h(DI)
18
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