TLV320AD543 Datasheet, PDF (18/35 Pages) Texas Instruments – Single Channel Data/Fax Codec

4.1.1 FS High Mode Primary Communication Timing
There are two possible modes for serial data transfer. One mode is the FS high mode, which is selected
by tying the SI_SEL terminal to DV_DD. Figure 4–2 shows the timing relationship for SCLK, FS, DOUT and
DIN in a primary communication when in FS high mode. The timing sequence for this operation is as follows:
1. FS is brought high and remains high for one SCLK period, then goes back low.
2. A 16-bit word is transmitted from the ADC (DT_DOUT) and a 16-bit word is received for DAC
conversion (DT_DIN).
DT_SCLK
DT_FS
DT_DIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DT_DOUT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 4–2. FS High Mode Primary Serial Communication Timing
4.2 FS Low Mode Primary Communication Timing
The second possible serial interface mode is the FS low mode which is selected by tying the SI_SEL terminal
to DV_SS. This mode differs from the FS high mode in that the frame sync signal (FS) is active low, data
transfer starts on the falling edge of FS, and FS remains low throughout the data transfer. Figure 4–3 shows
the timing relationship for SCLK, FS, DOUT, and DIN in a primary communication when in FS low mode.
The timing sequence for this operation is as follows:
1. FS is brought low by the TLV320AD543.
2. A 16-bit word is transmitted from the ADC (DT_DOUT) and a 16-bit word is received for DAC
conversion (DT_DIN).
3. FS is brought high signaling the end of the data transfer.
DT_SCLK
DT_FS
DT_DIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DT_DOUT
D15 D14 D13 D12 _{D11 D10} D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 4–3. FS Low Mode Primary Serial Communication Timing
4–2