TLV1504 Datasheet, PDF (18/42 Pages) Texas Instruments – 2.7 V TO 5.5 V, 10-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN

TLV1504, TLV1508
2.7 V TO 5.5 V, 10-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS251 – DECEMBER 1999
FIFO operation
ADC
10-BIT×8
FIFO
Serial
OD
76543210
FIFO Full
FIFO 1/2 Full
FIFO 3/4 Full
FIFO 1/4 Full
FIFO Threshold Pointer
Figure 15. TLV1504/TLV1508 FIFO
The device has an 8 layer FIFO that can be programmed for different thresholds. An interrupt is sent to the host
after the preprogrammed threshold is reached. The FIFO can be used to store data from either a fixed channel
or a series of channels based on a preprogrammed sweep sequence. For example, an application may require
eight measurements from channel 3. In this case, the FIFO is filled with 8 data sequentially taken from channel
3. Another application may require data from channel 0, channel 2, channel 4, and channel 6 in an orderly
manner. Therefore, the threshold is set for 1/2 and the sweep sequence 0–2–4–6–0–2–4–6 is chosen. An
interrupt is sent to the host as soon as all four data samples are in the FIFO.
SCLK and conversion speed
There are multiple ways to adjust the conversion speed.
D The SCLK can be used as the source of the conversion clock.
The onboard OSC is approximately 4 MHz and 13 conversion clocks are required to complete a conversion.
(Corresponding 3.25 µs conversion time). The devices can operate with an SCLK up to 20 MHz for the
supply voltage range specified. When a more accurate conversion time is desired, the SCLK can be used as
the source of the conversion clock. The clock divider provides speed options appropriate for an application
where a high speed SCLK is used for faster I/O. The total conversion time is 13 × (DIV/f_SCLK) where DIV is 1,
2, or 4. For example a 20 MHz SCLK with the divide by 4 option produces a {13 × (4/20 M) = 2.6 µs}
conversion time. When an external serial clock (SCLK) is used as the source of the conversion clock, the
maximum equivalent conversion clock (f_SCLK/DIV) should not exceed 6 MHz.
D Auto power down can be used. This mode is always on. If the device is not accessed (by CS or CSTART),
the converter is powered down to save power. The built-in reference is left on in order to quickly resume
operation within one half SCLK period. This provides unlimited choices to trade speed with power savings.
reference voltage
The device has a built-in reference with a programmable level of 2 V or 4 V. If the internal reference is used,
REFP is set to 2 V or 4 V and REFM is set to 0 V. An external reference can also be used through two reference
input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to
these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale
reading respectively. The values of REFP, REFM, and the analog input should not exceed the positive supply
or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale
when the input signal is equal to or higher than REFP and at zero when the input signal is equal to or lower than
REFM.
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