TC285SPD-B0 Datasheet, PDF (18/30 Pages) Texas Instruments – 1004 x 1002 PIXEL IMPACTRONTM CCD IMAGE SENSOR

TC285SPD-B0
1004 x 1002 PIXEL IMPACTRON^TM CCD IMAGE SENSOR
SOCS093 – JANUARY 2006
For optimum CCM operation, some overlap of CMG HIGH
and SRG1 HIGH is necessary. It is recommended to
design the timing such that phase can be easily adjusted by
at least 5ns.
CM G
SRG 1
SRG 2
RST
V out
Reference
Level
Output Signal(***)
SH
C lam p
(***) Output signal may not go all the way to zero. A zero offset of up to 100 mV may be present.
FIGURE 7. Detailed Serial Register Clock Timing for CDS Implementation.
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