LM34927_15 Datasheet, PDF (18/28 Pages) Texas Instruments – LM34927 Integrated Secondary-Side Bias Regulator for Isolated DC-DC Converters

LM34927
SNVS799G – APRIL 2012 – REVISED DECEMBER 2014
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8.2.1.2.8 Type III Feedback Ripple Circuit
Type III ripple circuit as described in Ripple Configuration is required for the Fly-Buck topology. Type I and Type
II ripple circuits use series resistance and the triangular inductor ripple current to generate ripple at V_OUT and the
FB pin. The primary ripple current of a Fly-Buck is the combination or primary and reflected secondary currents
as illustrated in Figure 20. In the Fly-Buck topology, Type I and Type II ripple circuits suffer from large jitter as the
reflected load current affects the feedback ripple.
V_OUT
L1
R_r
C_ac
To FB
C_r
R_FB2
R _FB1
C _OUT
GND
Figure 22. Type III Ripple Circuit
Selecting the Type III ripple components using the equations from Ripple Configuration will ensure that the FB
pin ripple is be greater than the capacitive ripple from the primary output capacitor C_OUT1. The feedback ripple
component values are chosen as shown in Equation 19.
C_r = 1000 pF
C_ac = 0.1 2F
( ) V_{IN (MIN)} - V_OUT x TON
R_rC_r @
50 mV
(19)
The calculated value for Rr is 66 kΩ. This value provides the minimum ripple for stable operation. A smaller
resistance should be selected to allow for variations in T_ON, C_OUT1 and other components. For this design, Rr
value of 46.4 kΩ is selected.
8.2.1.2.9 Secondary Diode
The reverse voltage across secondary-rectifier diode D1 when the high-side buck switch is off can be calculated
using Equation 20.
N2
V_D1 = _N1 V_IN
(20)
For a V_{IN_MAX} of 95 V and the 1:1 turns ratio of this design, a 100-V Schottky is selected.
8.2.1.2.10 V_CC and Bootstrap Capacitor
A 1-µF capacitor of 16 V or higher rating is recommended for the V_CC regulator bypass capacitor.
A good value for the BST pin bootstrap capacitor is 0.01-µF with a voltage rating of 16 or higher.
8.2.1.2.11 Input Capacitor
The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a
larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a
desired amplitude. For input ripple voltage ΔV_IN, C_IN can be calculated using Equation 21.
C_IN
³
I _OUT(MAX)
4 ´ f ´ DV_IN
(21)
Choosing a ΔV_IN of 0.5 V gives a minimum C_IN of 0.2 μF. A standard value of 0.47 μF is selected for C_BYP in this
design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the power
source to the converter. A standard value of 2.2 μF is selected for for C_IN in this design. The voltage ratings of
the two input capacitors should be greater than the maximum input voltage under all conditions.
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