DAC8571 Datasheet, PDF (18/28 Pages) Texas Instruments – 16-BIT, LOW POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

DAC8571
SLAS373A – DECEMBER 2002 – REVISED JULY 2003
www.ti.com
THEORY OF OPERATION (continued)
I²C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls
the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start
condition, and can only be asserted by the master. After the start condition, the master device puts out the
high-speed master code 0000 1xxx. No device is allowed to acknowledge the master code, but the devices are
required to switch their internal settings to support 3.4 Mbps operation upon the receipt of this code. After the
not-acknowledge signal, the master is allowed to operate at high speed. Now at much higher speed, the master
generates a repeated start condition. After the start condition, master generates the serial clock pulses and puts
out an address byte, ADDRESS<7:0>. While generating the bit stream, the master ensures the timing for valid
data. For each valid I²C bit, SDA line should remain stable during the entire high period of the SCL line. The
address byte consists of seven address bits and a direction bit (R/W=0). After sending the address byte, the
master generates a 9^th SCL pulse and monitors the state of the SDA line during the high period of this 9th clock
cycle (master leaves the SDA line high). The SDA line being pulled low by the receiver during the high period of
9^th clock cycle is called an acknowledge signal. If the master receives an acknowledge signal, it knows that a
DAC8571 successfully matched the address the master sent. Upon the receipt of this acknowledge, the master
knows that the high-speed communication link with a DAC8571 has been established and more data could be
sent. The master continues by sending a control byte, C<7:0>, which sets DAC8571 operation mode. After
sending the control byte, master expects an acknowledge. Upon the receipt of an acknowledge, the master
sends a most significant byte, M<7:0> that represents the eight most significant bits of DAC8571’s 16-bit
digital-to-analog conversion data. Upon the receipt of the M<7:0>, DAC8571 sends an acknowledge. After
receiving the acknowledge, the master sends a least significant byte, L<7:0>, that represents the eight least
significant bits of DAC8571’s 16-bit conversion data. After receiving the L<7:0>, the DAC8571 sends an
acknowledge. At the falling edge of the acknowledge signal following the L<0>, DAC8571 performs a digital to
analog conversion, depending on the operational mode. For further DAC updates, the master can keep repeating
M<7:0> and L<7:0> sequences, expecting an acknowledge after each byte. After the required number of digital
to analog conversions is complete, the master can break the communication link with DAC8571 by pulling the
SDA line from low to high while SCL line is high. This is called a stop condition. A stop condition brings the bus
back to idle (SDA and SCL both high). A stop condition indicates that communication with a device (DAC8571)
has ended. All devices on the bus including DAC8571 then await a new start condition followed by a matching
address byte. DAC8571 stays at its current state upon the receipt of a stop condition. A stop condition during the
high-speed mode also indicates the end of the high-speed mode. Table 3 demonstrates the sequence of events
that should occur while a master transmitter is writing to DAC8571 in I²C high-speed mode.
Table 3. Master Transmitter Writes to Slave Receiver in High-Speed Mode
HS Mode Write Sequence-Data Input
Transmitter MSB
6
5
4
3
2
1
Master
Start
Master
0
0
0
0
1
X
X
NONE
Not Acknowledge
Master
Master
DAC8571
Master
DAC8571
Master
DAC8571
Master
DAC8571
Master
Repeated Start
1
0
0
1
1
A0
0
DAC8571 Acknowledges
0
0
Load 1 Load 0
0
Brcsel
0
DAC8571 Acknowledges
D15
D14
D13
D12
D11
D10
D9
DAC8571 Acknowledges
D7
D6
D5
D4
D3
D2
D1
DAC8571 Acknowledges
Stop or Repeated Start ⁽²⁾
LSB
X
Comment
Begin sequence ⁽¹⁾
HS mode master code
No device may acknowledge HS
master code
R/W Write addressing (LSB = 0)
PD0 Control byte (PD0=0)
D8 Writing dataword, high byte
D0 Writing dataword, low byte
Done
(1) _{High-byte, low-byte sequences can repeat}
(2) _{Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.}
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