CC2541F128RHAR Datasheet, PDF (18/32 Pages) Texas Instruments – 2.4-GHz Bluetooth™ low energy and Proprietary System-on-Chip

CC2541
SWRS110D – JANUARY 2012 – REVISED JUNE 2013
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BLOCK DIAGRAM
A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
RESET_N
XOSC_Q2
XOSC_Q1
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
RESET
WATCHDOG TIMER
32-MHZ
CRYSTAL OSC
32.768-kHz
CRYSTAL OSC
CLOCK MUX and
CALIBRATION
DEBUG
INTERFACE
HIGH SPEED 32-kHz
RC-OSC RC-OSC
ON-CHIP VOLTAGE
REGULATOR
POWER-ON RESET
BROWN OUT
VDD (2 V–3.6 V)
DCOUPL
SLEEP TIMER
POWER MGT. CONTROLLER
8051 CPU
CORE
DMA
PDATA
XRAM
IRAM
SFR
UNIFIED
MEMORY
ARBITRATOR
RAM
SRAM
FLASH
FLASH
IRQ
CTRL
ANALOG COMPARATOR
OP-
DS ADC
AUDIO / DC
AES
ENCRYPTION
and
DECRYPTION
FIFOCTRL
FLASH CTRL
1-KB SRAM
RADIO
REGISTERS
Link Layer Engine
DEMODULATOR
MODULATOR
SDA
SCL
I²C
USART 0
USART 1
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
TIMER 3 (8-bit)
TIMER 4 (8-bit)
RECEIVE
TRANSMIT
RF_P RF_N
DIGITAL
ANALOG
MIXED
Figure 9. CC2541 Block Diagram
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