TMS320DM647_0804 Datasheet, PDF (173/182 Pages) Texas Instruments – Digital Media Processor

www.ti.com
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372B – MAY 2007 – REVISED APRIL 2008
Table 6-92. Switching Characteristics
Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module (see Figure 6-55)
NO.
1
t_{d(VCLKH-TXDI)}
1
t_{d(VCLKH-TXDI)}
2
t_{d(VCLKH-TXDV)}
PARAMETER
Delay time, VCLK high to VTXD[3:0] invalid [SLOW Mode]
Delay time, VCLK high to VTXD[3:0] invalid [FAST Mode]
Delay time, VCLK to VTXD[3:0] valid
-720
-900
MIN
MAX
2.25
0.86
6.85
UNIT
ns
ns
ns
Table 6-93. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-55)
NO.
RTM disabled
RTM enabled, RXD Flop = 0
RTM enabled, RXD Flop = 1
RTM enabled, RXD Flop = 2
3
t_{su(RXDV-VCLKH)}
Setup time, VRXD[3:0] valid before VCLK
high
RTM enabled, RXD Flop = 3
RTM enabled, RXD Flop = 4
RTM enabled, RXD Flop = 5
RTM enabled, RXD Flop = 6
RTM enabled, RXD Flop = 7
RTM disabled
RTM enabled, RXD Flop = 0
RTM enabled, RXD Flop = 1
RTM enabled, RXD Flop = 2
4
t_{h(VCLKH-RXDV)}
Hold time, VRXD[3:0] valid after VCLK high RTM enabled, RXD Flop = 3
RTM enabled, RXD Flop = 4
RTM enabled, RXD Flop = 5
RTM enabled, RXD Flop = 6
RTM enabled, RXD Flop = 7
-720
-900
MIN
0.2
1.25
0.91
0.64
0.36
0.09
-0.18
-0.44
-0.69
2
0.95
1.33
1.72
2.15
2.58
3.03
3.46
3.89
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
VCLK
2
VTXD[3:0]
VRXD[3:0]
Data
3
4
Data
Figure 6-55. VLYNQ Transmit/Receive Timing
Submit Documentation Feedback
Peripheral Information and Electrical Specifications 173