TRF6900A Datasheet, PDF (17/35 Pages) Texas Instruments – SINGLE-CHIP RF TRANSCEIVER

TRF6900A
SINGLE-CHIP RF TRANSCEIVER
SLAS258D – SEPTEMBER 2000 – REVISED SEPTEMBER 2001
general principles of DDS operation (continued)
The DDS constructs an analog sine waveform using an N-bit adder counting up from 0 to 2^N in steps of the
frequency register, whereby generating a digital ramp waveform. Each number in the N-bit output register is
used to select the corresponding sine wave value out of the sine lookup table. After the digital-to-analog
conversion, a low-pass filter is necessary to suppress unwanted spurious responses.
The analog output signal can be used as a reference input signal for a phase locked loop. The PLL circuit then
multiplies the reference frequency by a predefined factor.
TRF6900A direct digital synthesizer implementation
A block diagram of the DDS implemented in the TRF6900A is shown in Figure 16. It consists of a 24-bit
accumulator clocked by the reference oscillator along with control logic settings.
Reference Frequency, ƒ_ref
24
+
24-Bit
Register
11-Bit
DAC
11
Sine
Shaper
Low-Pass
Filter
ƒ_DDS
to
PLL
MODE – (Terminal 17)
A – Word
DDS Mode0
Frequency Setting
B – Word
DDS Mode1
Frequency Setting
DDS Frequency Register
22
24
22
Mode0/1
Select
+
Logic
Modulation
Control
Logic
TX_DATA – (Terminal 19)
D – Word / DEV Bits
(FSK Deviation)
FSK Frequency
Deviation Register 8
C – Word / MM Bit
(Modulation Mode Select)
Figure 16. DDS Block Diagram as Implemented in the TRF6900A
The frequency of the reference oscillator, ƒ_ref, is the DDS sample frequency, which also determines the
maximum DDS output frequency. Together with the accumulator width (in bits), the frequency resolution of the
DDS can be calculated. Multiplied by the divider ratio (prescaler) of the PLL, N, the minimum frequency step
size of the TRF6900A is calculated as follows:
Dƒ + N
ƒ_ref
2²⁴
The 24-bit accumulator can be programmed via two 22-bit frequency setting registers (the A-word determines
the mode0 frequency, the B-word determines the mode1 frequency) with the two MSB bits set to zero.
Consequently, the maximum bit weight of the DDS system is reduced to 1/8 (see Figure 17). This bit weight
corresponds to a VCO output frequency of (ƒ_ref/8) × N. Depending on the MODE terminal’s (terminal 17) logic
level, the internal mode select logic loads the frequency register with either the DDS_0 or DDS_1 frequency
(see Figure 16 and Figure 17).
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