TPS7A7300_15 Datasheet, PDF (17/29 Pages) Texas Instruments – 3-A, Fast-Transient, Low-Dropout Voltage Regulator

TPS7A7300
www.ti.com
SBVS190D – MARCH 2012 – REVISED SEPTEMBER 2013
DROPOUT VOLTAGE
The TPS7A7300 maintains its output voltage regulation with a dropout voltage (V_IN – V_OUT) greater than 0.24 V
under the test conditions specified in the Electrical Characteristics. In most power distribution tree (system)
designs, the TPS7A7300 can be used with a 0.3-V difference in the common voltage rails (for example, from 3.3
V_IN to 3.0 V_OUT, from 1.8 V_IN to 1.5 V_OUT, or from 1.5 V_IN to 1.2 V_IN).
INPUT CAPACITOR REQUIREMENTS
As a result of its very fast transient response and low-dropout operation support, it is necessary to reduce the
line impedance at the input pin of the TPS7A7300. The line impedance depends heavily on various factors, such
as wire (PCB trace) resistance, wire inductance, and/or output impedance of the upstream voltage supply (power
supply to the TPS7A7300). Therefore, a specific value for the input capacitance cannot be recommended until
the previously listed factors are finalized.
In addition, simple usage of large input capacitance is known to form unwanted LC resonance in combination
with input wire inductance. For example, a 5-nH inductor and a 10-µF input capacitor form an LC filter that has a
resonance at 712 kHz. This value of 712 kHz is well inside the bandwidth of the TPS7A7300 control loop.
The best guideline is to use a capacitor of up to 1 µF with well-designed wire connections (PCB layout) to the
upstream supply. In case it is difficult to optimize the input line, use a large tantalum capacitor in combination
with a good-quality, low-ESR, 1-µF ceramic capacitor.
OUTPUT CAPACITOR REQUIREMENTS
The TPS7A7300 is designed to be stable with standard ceramic capacitors with capacitance values from 4.7 μF
to 47 μF. The TPS7A7300 is evaluated using an X5R-type, 10-μF ceramic capacitor. X5R- and X7R-type
capacitors are highly recommended because they have minimal variation in value and ESR over temperature.
Maximum ESR should be below 1.0 Ω.
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude,
but increases duration of the transient response.
UNDERVOLTAGE LOCK-OUT (UVLO)
The TPS7A7300 uses an undervoltage lock-out circuit to keep the output shut off until the internal circuitry is
operating properly. The UVLO circuit has a deglitch feature that typically ignores undershoot of the input voltage
upon the event of device start-up. Still, a poor input line impedance may cause a severe input voltage drop when
the device powers on. As explained in the INPUT CAPACITOR REQUIREMENTS section, the input line
impedance should be well-designed.
SOFT-START
The TPS7A7300 has a SS pin that provides a soft-start (slow start) function.
By leaving the SS pin open, the TPS7A7300 performes a soft-start by its default setting.
As shown in Figure 1, by connecting a capacitor between the SS pin and the ground, the C_SS capacitor forms an
RC pair together with the integrated 50-kΩ resistor. The RC pair operates as an RC-delay circuit for the soft-start
together with the internal 700-µs delay circuit.
The relationship between C_SS and the soft-start time is shown in Figure 31 through Figure 33.
CURRENT LIMIT
The TPS7A7300 internal current limit circuitry protects the regulator during fault conditions. During a current limit
event, the output sources a fixed amount of current that is mostly independent of the output voltage. The current
limit function is provided as a fail-safe mechanism and is not intended to be used regularly. Do not design any
applications to use this current limit function as a part of expected normal operation. Extended periods of current
limit operation degrade device reliability.
Copyright © 2012–2013, Texas Instruments Incorporated
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