TPS54388-Q1_15 Datasheet, PDF (17/40 Pages) Texas Instruments – TPS54388-Q1 2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down SWIFT™ Switcher

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TPS54388-Q1
SLVSAF1D – OCTOBER 2010 – REVISED APRIL 2015
Device Functional Modes (continued)
vertical spacer
f_(SW) (kHz)
=
131 904 (MW/s)
Rt ^0.9492 (kW)
(9)
To reduce the solution size, one would typically set the switching frequency as high as possible, but consider
tradeoffs of the efficiency, maximum input voltage, and minimum controllable on-time.
The minimum controllable on-time is typically 60 ns at full-current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
8.4.6 Overcurrent Protection
The TPS54388-Q1 device implements a cycle-by-cycle current limit. During each switching cycle, the device
compares a voltage derived from the high-side switch current to the voltage on the COMP pin. When the
instantaneous switch-current voltage intersects the COMP voltage, the high-side switch turns off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,
increasing the switch current. An internal clamp on the error-amplifier output functions as a switch-current limit.
8.4.7 Frequency Shift
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54388-Q1
device implements a frequency shift. Without this frequency shift, during an overcurrent condition the low-side
MOSFET might not turn off long enough to reduce the current in the inductor, causing a current runaway. With
frequency shift, during an overcurrent condition there is a switching-frequency reduction from 100% to 50%, then
25%, as the voltage decreases from 0.8 V to 0 V on the VSENSE pin. The frequency shift allows the low-side
MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching frequency
increases as the voltage on VSENSE increases from 0 V to 0.8 V. See Figure 6 for details.
8.4.8 Reverse Overcurrent Protection
The TPS54388-Q1 device implements low-side current protection by detecting the voltage across the low-side
MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side
MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme,
the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased
outputs.
8.4.9 Synchronize Using the RT/CLK Pin
The RT/CLK pin synchronizes the converter to an external system clock. See Figure 29. To implement the
synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75 ns.
If the square wave pulls the pin above the PLL upper threshold, a mode change occurs, and the pin becomes a
synchronization input. The CLK mode disables the internal amplifier, and the pin becomes a high-impedance
clock input to the internal PLL. Stopping the clocking edges re-enables the internal amplifier, and the mode
returns to the frequency set by the resistor. The square-wave amplitude at this pin must transition lower than 0.6
V and higher than 1.6 V, typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge
of PH synchronizes to the falling edge of the RT/CLK pin.
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