TPS54360-Q1_15 Datasheet, PDF (17/43 Pages) Texas Instruments – TPS54360-Q1 4.5-V To 60-V Input, 3.5-A, Step-Down DC-DC Converter With Eco-Mode™

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Feature Description (continued)
f_{SW(max skip)}
=
1
t_ON
æ
´
ç
çè
I_O ´ R_dc + V_OUT + V_d
V_IN - I_O ´ R_DS(on) + V_d
ö
÷
÷ø
f_SW(shift) =
f_DIV
t_ON
´
æ
ç
çè
I_CL ´ R_dc + V_OUT(sc) + V_d
V_IN - I_CL ´ R_DS(on) + V_d
ö
÷
÷ø
TPS54360-Q1
SLVSBZ2A – SEPTEMBER 2013 – REVISED NOVEMBER 2014
(7)
(8)
I_O
I_CL
R_dc
V_IN
V_OUT
V_OUTSC
Vd
R_DS(on)
t_ON
ƒ_DIV
Output current
Current limit
inductor resistance
maximum input voltage
output voltage
output voltage during short
diode voltage drop
switch on resistance
minimum controllable on time
frequency divide equals (1, 2, 4, or 8)
7.3.11 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 26. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 1.7 V and
have a pulse-width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising
edge of the SW synchronizes to the falling edge of RT/CLK pin signal. The external synchronization circuit must
be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground when the
synchronization signal is off. When using a low impedance signal source, the frequency set resistor is connected
in parallel with an AC-coupling capacitor to a termination resistor (for example: 50 Ω) as shown in Figure 26. The
two resistors in series provide the default frequency setting resistance when the signal source is turned off. The
sum of the resistance should set the switching frequency close to the external CLK frequency. TI recommends to
AC couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin.
The first time the RT/CLK is pulled above the PLL threshold the TPS54360-Q1 switches from the RT resistor
free-running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and
the RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 µs. During the transition
from the PLL mode to the resistor programmed mode, the switching frequency falls to 150 kHz and then
increases or decreases to the resistor programmed frequency when the 0.5-V bias voltage is reapplied to the
RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB-pin voltage ramps from 0 to 0.8 V. The device
implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. Figure 27, Figure 28 and Figure 29 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
SPACER
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