TPS5430_15 Datasheet, PDF (17/36 Pages) Texas Instruments – TPS543x 3-A, Wide Input Range, Step-Down Converter

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TPS5430, TPS5431
SLVS632G – JANUARY 2006 – REVISED FEBRUARY 2015
Other capacitor types can be used with the TPS5430, depending on the needs of the application.
8.2.1.2.4 Output Voltage Set-Point
The output voltage of the TPS5430 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
R2
+
R1
VOUT
1.221
* 1.221
(12)
For any TPS5430 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ.
8.2.1.2.5 BOOT Capacitor
The BOOT capacitor should be 0.01 μF.
8.2.1.2.6 Catch Diode
The TPS5430 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is V_IN(MAX) + 0.5 V. Peak current must be greater than I_OUT(MAX) plus on half the peak
to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that
the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage
of 40 V, forward current of 3 A, and a forward voltage drop of 0.5 V.
8.2.1.2.7 Advanced Information
8.2.1.2.7.1 Output Voltage Limitations
Due to the internal design of the TPS543x, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
ǒǒ Ǔ Ǔ ǒ Ǔ V_OUTMAX + 0.87
V_INMIN * I_OMAX 0.230 ) V_D * I_OMAX R_L * V_D
(13)
Where
V_INMIN = minimum input voltage
I_OMAX = maximum load current
V_D = catch diode forward voltage.
R_L= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
ǒǒ Ǔ Ǔ ǒ Ǔ V_OUTMIN + 0.12
V_INMAX * I_OMIN 0.110 ) V_D * I_OMIN R_L * V_D
(14)
Where
V_INMAX = maximum input voltage
I_OMIN = minimum load current
V_D = catch diode forward voltage.
R_L= output inductor series resistance.
This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
carefully checked to assure proper functionality.
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