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TAS5729MD Datasheet, PDF (17/58 Pages) Texas Instruments – 12W I²S Input Class-D Amplifier with Digital Audio Processor and DirectPath™ HP / Line Driver
TAS5729MD
www.ti.com
SLOS836A – MAY 2013 – REVISED JUNE 2013
Theory of Operation and Detailed Description
POWER SUPPLY
To facilitate system design, the TAS5729MD needs only a single low-voltage DVDD supply in addition to the
higher-voltage PVDD power supply. An internal voltage regulator provides suitable voltage levels for the gate
drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges which operate in pairs to produce the full-bridge outputs capable
of driving BTL loads. For this reason, each half-bridge has separate bootstrap pins (BSTRPx) and power-stage
supply pins (PVDD). The gate drive voltage (GVDD_REG) is derived from the PVDD voltage. Special attention
should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general,
inductance between the power-supply pins and decoupling capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BSTRPx) to the power-stage output pin (SPK_OUTx). When the power-stage output is low, the bootstrap
capacitor is charged through an internal diode connected between the gate-drive regulator output pin
(GVDD_REG) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is
shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each pair of half-bridges has independent power-stage supply pins
(PVDD). For optimal electrical performance, EMI compliance, and system reliability, it is important that each
PVDD pin is decoupled with a ceramic capacitor placed as close as possible to each supply pin, as shown in the
typical application circuits.
ADR/SPK_FAULT
The ADR/SPK_FAULT pin is an input pin during power up. It can be pulled high or low through a pull-up or pull-
down resistor, as shown in the typical application circuit. HIGH sets an I²C address of 1010101[R/W] , and LOW
an address of 1010100[R/W] . Additionally, via the control port, it can be configured to serve as the fault indicator
for the speaker amplifier.
DEVICE PROTECTION SYSTEM
Overcurrent (OC) Protection With Current Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by a protection system. If a high-current condition persists, that is, the
power stage is being overloaded, a protection system triggers a shutdown, resulting in the power stage being set
in the high-impedance (Hi-Z) state. The device retries to start-up based on the retry time set in the BKDN_ERR
register and returns to normal operation once the fault condition (that is, a short circuit on the output) is removed.
Current limiting and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load
between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down. An
overcurrent fault error is reported in the ERROR STATUS register, and a fault error signal can be monitored on
the SPK_FAULT pin if configured in the SYSTEM CONTROL register.
Overtemperature Protection
The TAS5729MD has an overtemperature-protection system. If the device junction temperature exceeds the
amount specified by OTETHRES in the Protection Circuitry Electrical Characteristics table, the device is put into
thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state. The
TAS5729MD recovers automatically once the temperature drops by the amount specified by OTEHYST. An
overtemperature fault error is reported in the ERROR STATUS register, and a fault error signal can be monitored
on the SPK_FAULT pin if configured in the SYSTEM CONTROL register.
Copyright © 2013, Texas Instruments Incorporated
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