PCM1803A Datasheet, PDF (17/22 Pages) Texas Instruments – SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER

PCM1803A
www.ti.com
SLES142A – JUNE 2005 – REVISED AUGUST 2006
POWER DOWN
PDWN (pin 7) controls operation of the entire ADC. During power-down mode, supply current for the analog
portion is shut down and the digital portion is reset; also, DOUT (pin 12) is disabled. It is acceptable to halt the
system clock during power-down mode so that power dissipation is minimized. The minimum LOW pulse
duration on the PDWN pin is 100 ns.
It is recommended to set PWDN (pin 7) to LOW once to obtain stable analog performance when the sampling
rate, interface mode, data format, or oversampling control is changed.
PWDN
LOW
HIGH
Table 4. Power-Down Control
Power-Down Mode
Power-down mode
Normal operation mode
HPF BYPASS
The built-in function for dc-component rejection can be bypassed by BYPAS (pin 8) control. In bypass mode, the
dc component of the input analog signal, internal dc offset, etc., also are converted and included in the digital
output data.
BYPAS
LOW
HIGH
Table 5. HPF Bypass Control
HPF (High-Pass Filter) Mode
Normal (no dc component in DOUT) mode
Bypass (dc component in DOUT) mode
OVERSAMPLING RATIO CONTROL
OSR (pin 16) controls the oversampling ratio of the delta-sigma modulator, ×64 or ×128. The ×128 mode is
available for f_S ≤ 48 kHz.
OSR
LOW
HIGH
Table 6. Oversampling Control
Oversampling Ratio
×64
×128 (f_S ≤ 48 kHz)
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