LM3263 Datasheet, PDF (17/39 Pages) Texas Instruments – LM3263 High-Current Step-Down DC-DC Converter with MIPI® RF Front-End Control Interface for RF Power Amplifiers

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LM3263
SNVS837 – JUNE 2013
Shutdown
5 Ps (min)
VBATT
VIO
SDATA
VOUT
SW
Low Power
Initialization
50 Ps max
25 Ps max
Active
0V
APT
t0 ^{VBATT applied, VIO = 0V.}
LM3263 in Shutdown.
VIO applied.150ns later
LM3263 is in Low Power, and
t1
RFFE configuration writes may
occur.
Trigger is programmed. VSET and
t2 ^{SMPS_CFG loaded from shadow}
registers. LM3263 initializes and
powers up internal circuit blocks.
3.4V ^{t3 DC-DC is active in normal mode.}
Transmit Slot Boundary. DC-DC
t4 _{output settled (95%).}
t0
t1
t2
t3
t4
RFFE write
SMPS_CFG= auto PFM
(Reg 01h = 20h)
RFFE write
VSET = DC-DC VOUT
(Reg 03h = E3h)
RFFE write
PM_TRIG
(Reg 1Ch = 02h)
Figure 22. Triggered Startup Sequence
RFFE Interface
The Digital Control Serial Bus Interface provides MIPI RF Front-End Control Interface compatible access to the
programmable functions and registers on the device. The LM3263 uses a three-pin digital interface; two for
bidirectional communications between the IC’s connected to the bus, along with an interface voltage reference
VIO that also acts as asynchronous enable and reset. When VIO voltage supply is applied to the Bus, it enables
the Slave interface and resets the user-defined Slave registers to the default settings. The LM3263 can be set to
shutdown mode via the asynchronous VIO signal or low-power mode by setting the appropriate register via Serial
Bus Interface. The two communication lines are serial data (SDATA), and clock (SCLK). SCLK and SDATA must
be held low until VIO is present. The LM3263 connects as slave on a single-master Serial Bus Interface.
The SDATA signal is bidirectional, driven by the Master or a Slave. Data is written on the rising edge (transition
from logical level zero to logical level one) of the SCLK signal by both Master and Slaves. Master and Slave both
read the data on the falling edge (transition from logical level one to logical level zero) of the SCLK signal. A
logic-low level applied to VIO signal powers off the digital interface.
Supported Command Sequences
SCLK
SDATA
SSC
SA3
SA2
SA1
SA0
1
Slave Address
D6
D5
D4
D3
D2
D1
D0
P
0
Data
Parity
Bus
Park
Signal driven by Master.
Signal not driven; pull-down only.
For reference only.
Figure 23. Register 0 Write
Copyright © 2013, Texas Instruments Incorporated
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