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ADS8382 Datasheet, PDF (17/36 Pages) Texas Instruments – 600-kHz Sample Rate, ±1.25 LSB Typ, ±3 LSB Max INL, 18-Bit NMC Ensured Over Temperature
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ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
tw2
CS
tsu2
th1
CONVST
CONVST_QUAL
(Device Internal)
tquiet1
tsu4
td1
tquiet2
tsu1
tquiet1
tquiet2
SAMPLE
DEVICE STATE
td4
BUSY
CONVERT
tCONV
tquiet3
SAMPLE
tacq1
td2
Figure 43. Back-to-Back Conversion and Sample
3. Wait/Nap entry stimulus:
The device enters the wait or nap phase at the end of the conversion if the sample start command is not
given. This is shown in Figure 44.
CS
tsu4
tw2
th4
CONVST
CONVST_QUAL
(Device Internal)
tquiet1
tquiet2
tquiet1
tquiet2
DEVICE STATE
SAMPLE
BUSY
CONVERT
tCONV
tquiet3
WAIT
td2
SAMPLE
tacq1
Figure 44. Convert and Sample with Wait
If lower power dissipation is desired and throughput can be compromised, a nap state can be inserted in
between cycles (as shown in Figure 45). The device enters a low power (3 mA) state called nap if the end of
the conversion happens when CONVST_QUAL is low. The cost for using this special wait state is a longer
sampling time (tacq2) plus the nap time.
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