ADC104S101CIMM Datasheet, PDF (17/27 Pages) Texas Instruments – ADC104S101 4 Channel, 500 ksps to 1 Msps, 10-Bit A/D Converter

ADC104S101
www.ti.com
SNAS284F – FEBRUARY 2005 – REVISED MARCH 2013
APPLICATIONS INFORMATION
ADC104S101 OPERATION
The ADC104S101 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. Simplified schematics of the ADC104S101 in both track and hold modes
are shown in Figure 48 and Figure 49, respectively. In Figure 48, the ADC104S101 is in track mode: switch SW1
connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2 balances
the comparator inputs. The ADC104S101 is in this state for the first three SCLK cycles after CS is brought low.
Figure 49 shows the ADC104S101 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is
balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of
the analog input voltage. The ADC104S101 is in this state for the fourth through sixteenth SCLK cycles after CS
is brought low.
The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of
16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is
clocked into the DIN pin to indicate the multiplexer address for the next conversion.
IN1
MUX
IN4
SW1
SAMPLING
CAPACITOR
SW2
CHARGE
REDISTRIBUTION
DAC
+
CONTROL
-
LOGIC
AGND
V_A
2
Figure 48. ADC104S101 in Track Mode
IN1
MUX
IN4
SW1
SAMPLING
CAPACITOR
SW2
CHARGE
REDISTRIBUTION
DAC
+
CONTROL
-
LOGIC
AGND
V_A
2
Figure 49. ADC104S101 in Hold Mode
USING THE ADC104S101
An ADC104S101 timing diagram and a serial interface timing diagram for the ADC104S101 are shown in the
Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers.
SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data
output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the
ADC104S101's Control Register is placed on DIN, the serial data input pin. New data is written to the ADC at
DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when
CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a
power down state when CS is high, and also between continuous conversion cycles.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting on the 5th clock. If
there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK
after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK,
where "N" is an integer.
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