ADC102S021CIMM Datasheet, PDF (17/25 Pages) Texas Instruments – ADC102S021 2 Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter

ADC102S021
www.ti.com
SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting at the 5th clock. If
there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK
after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK,
where "N" is an integer.
When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the
subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC
enters the track mode on the first falling edge of SCLK after the falling edge of CS.
During each conversion, data is clocked into the ADC at DIN on the first 8 rising edges of SCLK after the fall of
CS. For each conversion, it is necessary to clock in the data indicating the input that is selected for the
conversion after the current one. See Table 3, Table 4, and Table 5.
If CS and SCLK go low within the times defined by t_CSU and t_CLH, the rising edge of SCLK that begins clocking
data in at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum
t_CSU and T_CLH times given in the Timing Specifications.
There are no power-up delays or dummy conversions required with the ADC102S021. The ADC is able to
sample and convert an input to full conversion immediately following power up. The first conversion result after
power-up will be that of IN1.
Bit 7 (MSB)
DONTC
Bit 6
DONTC
Bit 5
ADD2
Table 3. Control Register Bits
Bit 4
ADD1
Bit 3
ADD0
Bit 2
DONTC
Bit 1
DONTC
Bit 0
DONTC
Bit #:
7 - 6, 2 - 0
3
4
5
Symbol:
DONTC
ADD0
ADD1
ADD2
Table 4. Control Register Bit Descriptions
Description
Don't care. The value of these bits do not affect the device.
These bits determine which input channel will be sampled and converted in the next track/hold
cycle. The mapping between codes and channels is shown in Table 5.
ADD2
x
x
x
ADD1
0
0
1
Table 5. Input Channel Selection
ADD0
0
1
x
Input Channel
IN1 (Default)
IN2
Not allowed. The output signal at the D_OUT pin is indeterminate if ADD1 is high.
ADC102S021 TRANSFER FUNCTION
The output format of the ADC102S021 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC102S021 is V_A/1024. The ideal transfer characteristic is shown in
Figure 49. The transition from an output code of 00 0000 0000 to a code of 00 0000 0001 is at 1/2 LSB, or a
voltage of V_A/2048. Other code transitions occur at steps of one LSB.
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