VSP2232 Datasheet, PDF (16/19 Pages) Texas Instruments – CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS

VSP2232
SLAS320 – MAY 2001
timing specifications (continued)
SLOAD
t(XS)
SCLK
SDATA
t(CKH)
t(DS)
t(DH)
MSB
t(CKL)
t(CKP)
t(XH)
LSB
2-Bytes
PARAMETER
MIN TYP MAX UNIT
t(CKP) Clock period
100
ns
t(CKH) Clock high pulse width
40
ns
t(CKL) Clock low pulse width
40
ns
tsu
Data setup time
30
ns
th
Data hold time
30
ns
t(XS) SLOAD to SCLK setup time
30
ns
t(XH) SCLK to SLOAD hold time
30
ns
NOTES: 10. It is effective for the data shift operation at the rising edges of SCLK during SLOAD is low period. 2 bytes of data input are loaded
to the parallel latch in the VSP2232 at the rising edge of SLOAD.
11. When the input serial data is longer than 2 bytes (16 bits), the last 2 bytes become effective and the former bits are lost.
Figure 5. VSP2232 Serial Interface Timing Specification
16
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