TSB82AA2-EP Datasheet, PDF (16/102 Pages) Texas Instruments – 1394b OHCI-Lynx Controller Data Manual

The terminals are grouped in tables by functionality, such as PCI system function and power supply function (see
Table 2--3 through Table 2--7). The terminal numbers are also listed for convenient reference.
Table 2--3. Power Supply Terminals
TERMINAL
NAME
I/O
NO.
DESCRIPTION
GND
9, 22, 32, 43,
52, 63, 76, 81,
93, 103, 112, -- Ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane.
122, 127, 137,
140
REG18
16
87
The REG18 terminals are connected to the internal 1.8-V core voltage. They provide a mechanism to
-- provide local bypass for the internal core voltage or to externally provide the 1.8 V to the core if the internal
regulator is disabled.
REG_EN
2
Regulator enable. When this terminal is low, the internal regulator is enabled and generates the 1.8-V
I internal core voltage from the 3.3-V supply voltage. If it is disabled, then 1.8 V must be provided to the
REG18 terminals for normal operation.
V_CC
8, 15, 31, 42,
62, 75, 86,
102, 126, 135,
139
--
3.3-V power supply terminals. A parallel combination of high frequency decoupling capacitors near each
terminal is suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also
recommended. They must be tied to a low-impedance point on the circuit board.
V_CCP
21, 55, 91, 117
--
PCI signaling clamp voltage power input. PCI signals are clamped per the PCI Local Bus Specification. In
addition, if a 5-V ROM is used, then the V_CCP terminal must be connected to 5 V.
TERMINAL
NAME
NO.
G_RST
7
PCI_RST
6
MFUNC
1
SCL
3
SDA
4
Table 2--4. Reset and Miscellaneous Terminals
I/O
DESCRIPTION
Global power reset. This reset brings all of the TSB82AA2 internal registers to their default states, including those
registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional. A valid clock
input (PCI_CLK) is required before deasserting G_RST to reset some device functionality. Additionally, G_RST
I ^{must be asserted a minimum of 2 ms after both 3.3 V and 1.8 V are valid at the device.}
When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets to the
TSB82AA2 device. G_RST is designed to be a one-time power-on reset, and PCI_RST must be connected to the
PCI bus RST.
PCI reset. When this bus reset is asserted, the TSB82AA2 device places all output buffers in a high-impedance
I
state and resets all internal registers except device power management context and vendor-specific bits initialized
by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional. This terminal
must be connected to PCI bus RST.
Multifunction terminal. MFUNC is a multifunction terminal whose function is selected via the multifunction select
register:
Bits 2--0 Function
I/O
000
General-purpose input/output (GPIO)
001
CYCLEIN
010
CYCLEOUT
011
PCI_CLKRUN
100--111 Reserved
Serial clock. This terminal provides the SCL serial clock signaling.
I/O
ROM is implemented: Connect terminal 3 to the SCL terminal on the ROM; the 2.7-kΩ resistor pulls this signal
to the ROM V_CC. (SDA is implemented as open-drain.)
ROM is not implemented. Connect terminal 3 to ground with a 220-Ω resistor.
Serial data. This terminal provides the SDA serial data signaling. This terminal is sampled at G_RST to determine
if a serial ROM is implemented; thus if no ROM is implemented, then this terminal must be connected to ground.
I/O
ROM is implemented: Connect terminal 4 to the SDA terminal on the ROM; the 2.7-kΩ resistor pulls this signal
to the ROM V_CC. (SDA is implemented as open-drain.)
ROM is not implemented. Connect terminal 4 to ground with a 220-Ω resistor.
2--4