TPS77350 Datasheet, PDF (16/24 Pages) Texas Instruments – 250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
APPLICATION INFORMATION
external capacitor requirements (continued)
Ceramic capacitors have different types of dielectric material with each exhibiting different temperature and
voltage variation. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic type
capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable
over temperature (with the X7R being the more stable of the two) and are therefore acceptable to use. The Y5U
and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature;
therefore, the Y5U and Z5U are not generally recommended for use on this LDO. Independent of which type
of capacitor is used, one must make certain that at the worst case condition the capacitance/ESR meets the
requirement specified in Figures 18 – 21.
Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
IO
LDO
–
VESR ^RESR
+
+
VI
RLOAD ^VO
–
CO
Figure 22. LDO Output Stage With Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V_Cout = V_out). This means no current is flowing into the C_out
branch. If I_out suddenly increases (transient condition), the following occurs:
D The LDO is not able to supply the sudden current need due to its response time (t₁ in Figure 23). Therefore,
capacitor C_out provides the current for the new load condition (dashed arrow). C_out now acts like a battery
with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur
at R_ESR. This voltage is shown as V_ESR in Figure 22.
D When C_out is conducting current to the load, initial voltage at the load will be V_out = V_Cout – V_ESR. Due to
the discharge of C_out, the output voltage V_out will drop continuously until the response time t₁ of the LDO
is reached and the LDO will resume supplying the load. From this point, the output voltage starts rising again
until it reaches the regulated voltage. This period is shown as t₂ in Figure 23.
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
D The higher the ESR, the larger the droop at the beginning of load transient.
D The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.
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