TPS51285A Datasheet, PDF (16/32 Pages) Texas Instruments – Ultra-Low Quiescent (ULQ™) Dual Synchronous Step-Down Controller with 5V and 3.3V LDOs

TPS51285A
TPS51285B
SLVSBX0 – APRIL 2013
www.ti.com
Output Overvoltage and Undervoltage Protection
TPS51285A and TPS51285B assert the overvoltage protection (OVP) when VFBx voltage reaches OVP trip
threshold level. When an OVP event is detected, the controller changes the output target voltage to 0 V. This
usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the low-side
MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on. After the on-time expires,
DRVH is turned off and DRVL is turned on again. This action minimizes the output node undershoot due to LC
resonance. When the VFBx reaches 0 V, the driver output is latched as DRVH off and DRVL on. The
undervoltage protection (UVP) latch is set when the VFBx voltage remains lower than UVP trip threshold voltage
for 250 μs or longer. In this fault condition, the controller latches DRVH low and DRVL low and discharges the
outputs through VO1(CH1) and SW2 (CH2). UVP detection function is enabled after 1.1 ms of SMPS operation
to ensure startup. Toggle ENx to clear the fault latch.
Undervoltage Lockout (UVLO) Protection
TPS51285A and B have undervoltage lock out protection at VIN, VREG5 and VREG3. When each voltage is
lower than their UVLO threshold voltage, both SMPS are shut-off. They are non-latch protections.
Over-Temperature Protection
TPS51285A and TPS51285B features an internal temperature monitor. If the temperature exceeds the threshold
value (typically 140°C), the device is shut off including LDOs. This is non-latch protection.
REFERENCE DESIGN
Application Schematic
This session describes a simplified design procedure for 5 V and 3.3 V outputs application using TPS1285A and
TPS1285B. Figure 6 shows the application schematic.
V_IN
U1
C2
C1
L1
V_OUT
5V
C3
R1
R2
12 VIN
Q1
R7 _C7
C8
R8
17 VBST1
VBST2 9
R9
R10
16 DRVH1 DRVH2 10
18 SW1
SW2 8
R3
EN 5V
VREG5
(5-V LDO)
R11
15 DRVL1
14 VO1
DRVL2 11
2 VFB1
VFB2 4
1 CS1
CS2 5
19 VCLK
20 EN1
13 VREG5
PGOOD 7
EN2 6
VREG3 3
GND
Thermal-Pad
C5
R6
C6
Q2
L2
V_OUT
3.3 V
C4
R4
PGOOD
EN 3.3 V
VREG3
(3.3-V LDO)
R5
Figure 6. Application Schematic
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