TMS626162A Datasheet, PDF (16/44 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
(see Note 3)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = – 2 mA
VOL
II
IO
Low-level output voltage
Input current (leakage)
Output current (leakage)
ICC1 Operating current
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
Precharge standby current in power-down mode
Precharge standby current in non-power-down mode
Active standby current in power-down mode
Active standby current in non-power-down mode
IOL = 2 mA
0 V ≤ VI ≤ VCC + 0.3 V, All other pins = 0 V to VCC
0 V ≤ VO ≤ VCC + 0.3 V, Output disabled
w Burst length = 1, tRC tRC MIN
CAS latency = 2
IOH/IOL = 0 mA, one bank activated (see Note 4) _{CAS latency = 3}
v CKE VIL MAX, tCK = 15 ns (see Note 5)
v CKE and CLK VIL MAX, tCK = ∞ (see Note 6)
w CKE VIH MIN, tCK = 15 ns (see Note 5)
w v CKE VIH MIN, CLK VIL MAX, tCK= ∞ (see Note 6)
v CKE VIL MAX, tCK = 15 ns (see Note 5)
v CKE and CLK VIL MAX, tCK = ∞ (see Note 6)
w CKE VIH MIN, tCK = 15 ns (see Note 5)
w v CKE VIH MIN, CLK VIL MAX tCK = ∞ (see Note 6)
ICC4 Burst current
Page burst, IOH/IOL = 0 mA
CAS latency = 2
All banks activated, nCCD = one cycle (see Note 7) _{CAS latency = 3}
ICC5
ICC6
Auto-refresh current
Self-refresh current
w tRC tRC MIN
v CKE VIL MAX
CAS latency = 2
CAS latency = 3
NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
4. Control, DQ, and address inputs change twice during tRC.
5. Control, DQ, and address inputs change state once every 30 ns.
6. Control, DQ, and address inputs do not change (stable).
7. Control, DQ, and address inputs change state once every cycle.
’626162A-10
MIN MAX
2.4
0.4
±10
±10
105
115
2
2
25
2
3
3
30
15
110
140
85
95
2
UNIT
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA