TMS320C6474_1 Datasheet, PDF (16/41 Pages) Texas Instruments – Digital Signal Processor Silicon Revisions 1.3, 1.2

Silicon Revision 1.3 Known Design Exceptions to Functional Specifications
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Advisory 1.3.3
Potential Insertion or Deletion of 2 Bits in SerDes Data Stream
Revision(s) Affected:
Details:
Workarounds:
1.3, 1.2
For arbitrary phase mode, a FIFO function is integrated into the SerDes TX serializer.
This FIFO has three states (minus1, center, plus1) and is supposed to be reset to the
center state at startup. From this position, the SerDes is then tolerant to variations of
phase between the input clock (TXBCLKIN) and the SerDes internal clock, caused by
temperature and voltage variations. However, as a result of a logic bug, the possibility
exists that under some circumstances, the FIFO may not start in the center state. When
this happens, there is a risk that the FIFO may subsequently overflow or underflow.
Whether the FIFO fails to initialize to the center state depends on the timing
relationships between several signals, including the SerDes internal clock. Even if the
FIFO fails to initialize to the center state, the FIFO will only underflow or overflow if the
phase relationship between the TXBCLKIN input and the internal SerDes clock vary (due
to temperature or voltage changes) in such a way as to cause their edges to cross in
one particular direction. Overflow results in two bits being added to the data stream.
Underflow results in two bits being deleted. If overflow or underflow occurs at all, it only
happens once per TX lane because after it has occurred the FIFO is configured exactly
as if it had initialized to the center state at startup.
The precise silicon process of the device will also be a factor in whether the overflow or
underflow occurs. Some devices may exhibit this behavior at some particular PVT
combinations, others may never exhibit it. It is not possible to predict whether, or under
what conditions, a device is susceptible. If overflow or underflow occur, it could be at any
time ranging from immediately after startup to weeks, months, or years later.
The issue can be worked around by software control of two ports on the SerDes. At
initialization, cycling of bits resets the circuit and resolves the issue.
• AIF has a software workaround as follows:
The software workaround limits restart to per macro, not per lane. There is one set of
software control bits for the B8 and another for the B4. For details, see the
device-specific data manual, TMS320C6474 Multicore Digital Signal Processor
(literature number SPRS552). There are new recommendations for the initialization
sequence that is shown in the following code example:
//Enable the Tx Link
CSL_FINST(hAifLink[0]->regs->LCFG[1].LINK_CFG, AIF_LINK_CFG_TX_LINK_EN, ENABLED);
//Set the Link Rate
if (aCommoncfg[0].linkRate == CSL_AIF_LINK_RATE_1x){
CSL_FINST(hAifLink[0]->regs->LCFG[1].LINK_CFG, AIF_LINK_CFG_LINK_RATE, 1X);
}
else if (aCommoncfg[0].linkRate == CSL_AIF_LINK_RATE_2x)
{
CSL_FINST(hAifLink[0]->regs->LCFG[1].LINK_CFG, AIF_LINK_CFG_LINK_RATE, 2X);
}
else if (aCommoncfg[0].linkRate == CSL_AIF_LINK_RATE_4x)
{
CSL_FINST(hAifLink[0]->regs->LCFG[1].LINK_CFG, AIF_LINK_CFG_LINK_RATE, 4X);
}
//Toggle the ENFTP bit
CSL_FINS( hAifLink[0]->regs->AI_SERDES0_TST_CFG, AIF_AI_SERDES0_TST_CFG_INVPATT,
1);
CSL_FINS(hAifLink[0]->regs->AI_SERDES0_TST_CFG, AIF_AI_SERDES0_TST_CFG_INVPATT,
0);
CSL version 3.0.6.2 for the C6474 device has a new hardware control command
(CSL_AIF_CMD_ENABLE_DISABLE_TX_LINK_SI1_1) that has the fix for this
advisory.
16
TMS320C6474 DSP
Silicon Revisions 1.3, 1.2
SPRZ283 – October 2008
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