TLV990-28 Datasheet, PDF (16/22 Pages) Texas Instruments – 3-V, 10-BIT, 28-MSPS AREA CCD ANALOG FRONT END

TLV990Ć28
3ĆV, 10ĆBIT, 28ĆMSPS AREA CCD ANALOG FRONT END
SLAS300A − AUGUST 2000 − REVISED MARCH 2004
PRINCIPLES OF OPERATION
CDS and PGA
The output from the CCD sensor is first fed to a correlated double sampler (CDS) through the CCDIN pin. The
CCD signal is sampled and held during the reset-reference interval and the video-signal interval. By subtracting
two resulting voltage levels, the CDS removes low-frequency noise from the output of the CCD sensor and
obtains the voltage difference between the CCD reference level and the video level of each pixel. Two
sample/hold control pulses (SR and SV) are required to perform the CDS function.
The CCD output is capacitively coupled to the TLV990-28. The ac-coupling capacitor is clamped to establish
proper dc bias during the dummy pixel interval by the CLCCD input. The bias at the input to the TLV990-28 is
set to 1.2 V. Normally, CLCCD is applied at the sensor’s line rate. A capacitor, with a value ten times larger than
that of the input ac-coupling capacitor, should be connected between the CLREF pin and AGND.
When operating the TLV990-28 at its maximum speed, the CCD internal source resistance should be smaller
than 50 Ω. Otherwise CCD output buffering is required.
The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 to 36 dB
by programming the internal-gain register via the serial port. The PGA is digitally controlled with 10-bit resolution
on a linear dB scale, resulting in a 0.045-dB gain step. The gain can be expressed by the following equation,
Gain = PGA code × 0.045 dB
Where PGA code has a range of 0 to 767.
ADC
The ADC employs a pipelined architecture to achieve high throughput and low-power consumption. Fully-
differential implementation and digital-error correction ensure 10-bit resolution.
The latency of the ADC data output is 6 ADCCLK cycles, as shown in Figure 1. Pulling the OE pin (pin 24) high
puts the ADC output in high impedance.
user DACs
The TLV990-28 includes two user DACs that can be used for external analog settings. The output voltage of
each DAC can be independently set and has a range of 0 V up to the supply voltage, with an 8-bit resolution.
When the user DACs are not used in a camera system, they can be put in the standby mode by programming
control bits in the control register.
internal timing
The SR and SV signals are required to operate the CDS, as previously explained. The user needs to
synchronize the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to external
circuitry by the ADCCLK signal, which is also used internally to control both ADC and PGA operations. The
positive-half cycle of the ADCCLK signal is required to always fall in between two adjacent SV pulses as shown
in Figure 1. The user can then fine tune the ADCCLK timing in relation to the CDS timing to achieve optimal
performance.
The CLCCD signal is used to activate the input clamping and the OBCLP signal is used to activate auto-optical
black and offset correction.
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