PCM1780 Datasheet, PDF (16/31 Pages) Texas Instruments – 24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma, Audio Digital-to-Analog Converter

PCM1780, PCM1781, PCM1782
SLES132A – MARCH 2005 – REVISED APRIL 2005
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OVERSAMPLING RATE CONTROL
The PCM1780/81/82 automatically controls the oversampling rate of the delta-sigma D/A converters with the
system clock frequency. The oversampling rate is set to 64× oversampling with an 1152-f_S, 768-f_S, or 512-f_S
system clock, to 32× oversampling with a 384-f_S or 256-f_S system clock, or to 16× oversampling with a 192-f_S or
128-f_S system clock.
ZERO FLAGS (PCM1780/82)
Zero-Detect Condition
Zero detection for each output channel is independent from the other. If the data for a given channel remains at a
0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.
Zero-Flag Outputs
Each channel has a corresponding zero-flag pin, ZEROL (pin 1) or ZEROR (pin 16). Given that a zero-detect
condition exists for one or more channels, the zero-flag pins for those channels are set to a logic-1 state. The
zero-flag pins can be used to operate external mute circuits, or used as status indicators for a microcontroller,
audio signal processor, or other digitally controlled function.
The active polarity of the zero-flag outputs can be inverted by setting the ZREV bit of control register 22 to 1. The
reset default is active-high output, or ZREV = 0.
The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register 22
to 1. The reset default is for independent L-channel and R-channel zero flags, or AZRO = 0.
On the PCM1782, ZEROL and ZEROR are open-drain outputs.
ZERO FLAG (PCM1781)
The PCM1781 has a zero-flag pin, ZEROA (pin 16). ZEROA is the L-channel and R-channel common zero-flag
pin. If the data for L-channel and R-channel remains at a 0 level for 1024 sampling periods (or LRCK clock
periods), ZEROA is set to a logic-1 state.
HARDWARE CONTROL (PCM1781)
The digital functions of the PCM1781 are capable of hardware control. Table 2 shows selectable formats, Table 3
shows de-emphasis control, and Table 4 shows muting control.
Table 2. Data Format Selection
FMT (PIN 1)
LOW
HIGH
DATA FORMAT
16- to 24-bit, I²S format
16-bit right-justified
DEMP1 (PIN 3)
LOW
LOW
HIGH
HIGH
Table 3. De-Emphasis Control
DEMP0 (PIN 2)
LOW
HIGH
LOW
HIGH
DE-EMPHASIS FUNCTION
OFF
48-kHz de-emphasis ON
44.1-kHz de-emphasis ON
32-kHz de-emphasis ON
Table 4. Mute Control
MUTE (PIN 4)
LOW
HIGH
MUTE STATUS
Mute OFF
Mute ON
16