ADS8505 Datasheet, PDF (16/25 Pages) Texas Instruments – 16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER

ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
www.ti.com
APPLICATION INFORMATION (continued)
CAP
CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF capacitor can be placed between the CAP pin
and ground. Because the internal reference buffer is internally compensated, the external capacitor is not
necessary for compensation of the reference buffer. This relaxes the performance requirements of the capacitor
and makes the performance of the ADC less sensitive to the capacitor.
The output of the buffer is capable of driving up to 2 mA of current to a dc load. A dc load requiring more than 2
mA of current from the CAP pin begins to degrade the linearity of the ADS8505. Using an external buffer allows
the internal reference to be used for larger dc loads and ac loads. Do not attempt to directly drive an ac load
with the output voltage on CAP. This causes performance degradation of the converter.
LAYOUT
POWER
For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the
analog and digital grounds together. As noted in the electrical specifications, the ADS8505 uses 90% of its
power for the analog circuitry. The ADS8505 should be considered as an analog component.
The +5-V power for the A/D should be separate from the +5 V used for the system's digital logic. Connecting
V_DIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital
logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest
of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used.
Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter
the supply. Either using a filtered digital supply or a regulated analog supply, both V_DIG and V_ANA should be tied
to the same +5-V source.
GROUNDING
Three ground pins are present on the ADS8505. DGND is the digital supply ground. AGND2 is the analog
supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more
susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
All the ground pins of the A/D should be tied to the analog ground plane, separated from the system's digital
logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the
system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample/hold on many CMOS A/D converters release a significant amount of
charge injection which can cause the driving op-amp to oscillate. The FET switch on the ADS8505, compared to
the FET switches on other CMOS A/D converters, releases 5% to 10% of the charge. There is also a resistive
front end which attenuates any charge which is released. The end result is a minimal requirement for the
anti-alias filter on the front end. Any op-amp sufficient for the signal in an application is sufficient to drive the
ADS8505.
The resistive front end of the ADS8505 also provides an assured ±25-V overvoltage protection. In most cases,
this eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS8505 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus
is to be active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to
isolate the A/D from other peripherals on the same bus. The 3-state outputs can also be used when the A/D is
the only peripheral on the data bus.
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