OMAP-L138 Datasheet, PDF (157/255 Pages) Texas Instruments – OMAP-L138 Low-Power Applications Processor

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OMAP-L138 Low-Power Applications Processor
SPRS586 – JUNE 2009
Table 6-73. Additional⁽¹⁾ SPI1 Master Timings, 5-Pin Option⁽²⁾⁽³⁾
NO.
PARAMETER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
18 t_{d(SPC_ENA)M}
Max delay for slave to deassert SPI1_ENA after final
SPI1_CLK edge to ensure master does not begin the next
transfer. ⁽⁴⁾
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
20 t_{d(SPC_SCS)M}
Delay from final SPI1_CLK edge to
master deasserting SPI1_SCS ⁽⁵⁾⁽⁶⁾
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Max delay for slave SPI to drive SPI1_ENA valid after master asserts SPI1_SCS to
21 t_{d(SCSL_ENAL)M} delay the
master from beginning the next transfer,
Polarity = 0, Phase = 0,
to SPI1_CLK rising
22 t_{d(SCS_SPC)M} Delay from SPI1_SCS active to first SPI1_CLK^(7)(8)(9)
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
1.2V
MIN
MAX
0.5M+P+5
1.1V
MIN
MAX
0.5M+P+5
1.0V
MIN
MAX
UNIT
0.5M+P+6
P+5
0.5M+P+5
P+5
0.5M+P+5
P+6
ns
0.5M+P+6
P+5
P+5
P+6
0.5M+P-1
0.5M+P-5
0.5M+P-6
P-1
P-5
P-6
ns
0.5M+P-1
0.5M+P-5
0.5M+P-6
P-1
P-5
P-6
C2TDELAY+P
C2TDELAY+P
C2TDELAY+P ns
2P-1
2P-5
2P-6
0.5M+2P-1
0.5M+2P-5
0.5M+2P-6
ns
2P-1
2P-5
2P-6
0.5M+2P-1
0.5M+2P-5
0.5M+2P-6
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-70).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
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Peripheral Information and Electrical Specifications 157