UCD7242 Datasheet, PDF (15/32 Pages) Texas Instruments – Digital Dual Synchronous-Buck Power Driver

UCD7242
www.ti.com
SLUS962 – JANUARY 2010
VGG_DIS
This pin, when asserted high, disables the on-chip V_GG linear regulator. When tied low, the VGG linear regulator
is used to derive V_GG from V_IN. This pin is designed to be permanently tied high or low depending on the power
architecture being implemented. It is not intended to be switched dynamically while the device is in operation.
SW
The SW pin is the switching node of the power conversion stage. When configured as a synchronous buck, the
voltage swing on SW normally traverses from slightly below ground to above V_IN. Parasitic inductance in the
high-side FET conduction path and the output capacitance (Coss) of the low side FET form a resonant circuit
than can produce high frequency ( > 100MHz) ringing on this node. The voltage peak of this ringing will exceed
V_IN. Care must be taken not to exceed the maximum voltage rating of this pin. The main areas available to
impact this amplitude are: the driver voltage magnitude (V_GG) and the parasitic source and return paths for the
MOSFET (V_IN, PGND). In some cases, a series resistor and capacitor snubber network connected from this pin
to PGND can be helpful in damping the ringing and decreasing the peak amplitude. In general this should not be
necessary due to the integrated nature of this part.
BST
The BST pin provides the drive voltage for the high-side FET. A bootstrap capacitor is connected from this pin to
the BST-SW node. Internally, a diode connects the BST pin to the V_GG supply. In normal operation, when the
high side FET is off and the low-side FET is on, the SW node is pulled to ground and, thus, holds one side of the
bootstrap capacitor at ground potential. The other side of the bootstrap capacitor is clamped by the internal diode
to VGG. The voltage across the bootstrap capacitor at this point is the magnitude of the gate drive voltage
available to switch-on the high-side FET. The bootstrap capacitor should be a low ESR ceramic type, a minimum
value of 0.22mF is recommended.
In order to ensure that the bootstrap capacitor has sufficient time to recharge, the steady-state duty cycle must
not exceed what is shown in Figure 13. The curve in Figure 13 is for C_BST= 0.22µF. Different values of C_BST will
have different DMAX limitations.
96
94
92
90
88
86
0.6 0.8
1
1.2 1.4 1.6 1.8
2
f_s - Switching Frequency - MHz
Figure 13.
BST-SW
Electrically this node is the same as the SW pin. However, it is physically closer to the BST pin so as to minimize
parasitic inductance effects of trace routing to the BST capacitor. Keeping the external traces short should
minimize turn on and off times.
This pin is not sized for conducting inductor current and should not be tied to the SW pin. It is only for the BST
pin capacitor connection.
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