TPS7A6933QDRQ1 Datasheet, PDF (15/26 Pages) Texas Instruments – High-Voltage Ultralow-Iq Low-Dropout Regulator

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TPS7A6601-Q1, TPS7A6633-Q1
TPS7A6650-Q1, TPS7A6933-Q1
TPS7A6950-Q1
SLVSBL0B – DECEMBER 2012 – REVISED AUGUST 2013
LAYOUT INFORMATION
Package Mounting
Solder pad footprint recommendations for the TPS7A66xx-Q1 and TPS7A69xx-Q1 are available at the end of
this product data sheet and at www.ti.com.
Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board
design with separate ground planes for Vin and Vout, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of
the device.
Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.
Place every capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces because they may impact system performance negatively
and even cause instability.
If possible, and to ensure the maximum performance specified in this product data sheet, use the same layout
pattern used for the TPS7A66xx-Q1 and TPS7A69xx-Q1 evaluation board, available at www.ti.com.
Additional Layout Considerations
The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple
undesirable signals from nearby components (especially from logic and digital ICs, such as microcontrollers and
microprocessors); these capacitive-coupled signals may produce undesirable output voltage transients. In these
cases, TI recommends the use of a fixed-voltage version of the TPS7A66xx-Q1, or isolation of the FB node by
flooding the local PCB area with ground-plane copper to minimize any undesirable signal coupling.
Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the
device to cool. Cooling of the junction temperature to approximately 150°C enables the output circuitry.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat-spreading area. For reliable operation, junction temperature should be limited to a maximum of 125°C at the
worst-case ambient temperature for a given application. To estimate the margin of safety in a complete design
(including the copper heat-spreading area), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at
least 45°C above the maximum expected ambient condition of the particular application. This configuration
produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-
case load.
The purpose of the design of the internal protection circuitry of the TPS7A66/69xx-Q1 is for protection against
overload conditions, not as a replacement for proper heat-sinking. Continuously running the TPS7A66xx-Q1 or
TPS7A69xx-Q1 into thermal shutdown degrades device reliability.
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
• Added two conditions to Vdropout in the Electrical Characteristics table ............................................................................. 3
Copyright © 2012–2013, Texas Instruments Incorporated
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Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1