TPS61240-Q1_15 Datasheet, PDF (15/25 Pages) Texas Instruments – 3.5-MHz High Efficiency Step-Up Converter

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TPS61240-Q1
SLVSAO4 – DECEMBER 2010
INPUT CAPACITOR
At least 2.2mF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior
of the total power supply circuit. It is recommended to place a ceramic capacitor as close as possible to the VIN
and GND pins
OUTPUT CAPACITOR
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
V_OUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is recommended.
This small capacitor should be placed as close as possible to the V_OUT and GND pins of the IC. To get an
estimate of the recommended minimum output capacitance, Equation 5 can be used.
( ) _{Cmin =}
I_OUT ´ V_OUT - V_IN
f ´ DV ´ V_OUT
(5)
Parameter f is the switching frequency and ΔV is the maximum allowed ripple.
With a chosen ripple voltage of 10 mV, a minimum effective capacitance of 2.7 mF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using
ΔV_ESR = I_OUT x R_ESR
A capacitor with a value in the range of the calculated minimum should be used. This is required to maintain
control loop stability. There are no additional requirements regarding minimum ESR. There is no upper limit for
the output capacitance value. Larger capacitors cause lower output voltage ripple as well as lower output voltage
drop during load transients.
Note that ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective
capacitance needed. Therefore the right capacitor value has to be chosen carefully. Package size and voltage
rating in combination with material are responsible for differences between the rated capacitor value and the
effective capacitance.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, I_L
• Output ripple voltage, V_O(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. V_O immediately shifts by an amount equal to ΔI_(LOAD) × ESR, where ESR is
the effective series resistance of C_O. ΔI_(LOAD) begins to charge or discharge C_O generating a feedback error
signal used by the regulator to return V_O to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode. During this recovery time, V_O can be monitored for settling time, overshoot or
ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase
margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g.,
MOSFET r_DS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage
range, load current range, and temperature range.
Copyright © 2010, Texas Instruments Incorporated
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