SN74GTLP2033 Datasheet, PDF (15/20 Pages) Texas Instruments – 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tr
FROM
(INPUT)
AI
(buffer)
AI
(buffer)
LEAB
(latch mode)
LEAB
(latch mode)
CLKAB
(flip-flop mode)
CLKAB
(flip-flop mode)
OMODE
TO
(OUTPUT)
B
B
B
B
B
B
B
OMODE
B
Rise time, B-port outputs (20% to 80%)
tf
Fall time, B-port outputs (80% to 20%)
† _{Slow (ERC = H) and Fast (ERC = L)}
‡ _{All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.}
EDGE RATE^†
Slow
Fast
Slow
Fast
Slow
Fast
Slow
Fast
Slow
Fast
Slow
Fast
TYP^‡ UNIT
4.7
ns
5
3.7
ns
4
5.5
ns
5.8
4.6
ns
4.8
5.8
ns
6
4.9
ns
4.9
5.5
ns
5.7
4.5
ns
4.7
1.8
ns
1.1
3.4
ns
2.6
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