MSP430X461X1 Datasheet, PDF (15/92 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430x461x1, MSP430x461x
MIXED SIGNAL MICROCONTROLLER
interrupt vector addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
NMI
Oscillator Fault
Flash Memory Access Violation
WDTIFG
KEYV
(see Note 1 and 5)
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2, and 5)
Reset
0FFFEh 31, highest
(Non)maskable
(Non)maskable
0FFFCh
30
(Non)maskable
Timer_B7
Timer_B7
TBCCR0 CCIFG0 (see Note 2)
TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (see Notes 1 and 2)
Maskable
Maskable
0FFFAh
29
0FFF8h
28
Comparator_A
Watchdog Timer+
USCI_A0/USCI_B0 Receive
USCI_A0/USCI_B0 Transmit
ADC12 (see Note 6)
Timer_A3
Timer_A3
CAIFG
WDTIFG
UCA0RXIFG, UCB0RXIFG (see Note 1)
UCA0TXIFG, UCB0TXIFG (see Note 1)
ADC12IFG (see Notes 1 and 2)
TACCR0 CCIFG0 (see Note 2)
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF6h
27
0FFF4h
26
0FFF2h
25
0FFF0h
24
0FFEEh
23
0FFECh
22
0FFEAh
21
I/O Port P1 (Eight Flags)
USART1 Receive
USART1 Transmit
I/O Port P2 (Eight Flags)
Basic Timer1/RTC
DMA
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
URXIFG1
UTXIFG1
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
BTIFG
DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 1 and 2)
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFE8h
20
0FFE6h
19
0FFE4h
18
0FFE2h
17
0FFE0h
16
0FFDEh
15
Reserved
Reserved
Reserved
Reserved (see Note 4)
Maskable
0FFDCh
0FFDAh
...
0FFC0h
14
13
...
0, lowest
NOTES:
1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
5. Access and key violations, KEYV and ACCVIFG, only applicable to F devices.
6. ADC12 is not implemented in MSP430x461x1 devices.
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