INA203_15 Datasheet, PDF (15/37 Pages) Texas Instruments – INA20x Unidirectional Measurement Current-Shunt Monitor With Dual Comparators

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Feature Description (continued)
INA203, INA204, INA205
SBOS393E – MARCH 2007 – REVISED NOVEMBER 2015
Load Supply
-18V to +80V
R_SHUNT
3mW
Current Shunt
Monitor Output
C_BYPASS
0.01mF
V_S
OUT
CMP1 IN-/0.6 REF
CMP1 IN+
CMP2 IN+
CMP2 IN-/0.6 REF
GND
INA203
x20
1.2V REF
V_IN+
V_IN-
1.2V REF OUT
CMP1 OUT
CMP2 OUT
CMP2 DELAY
CMP1 RESET
Transparent/Reset
R_PULL-UP
4.7kW
Optional Delay
Capacitor
0.2mF
Latch
R_PULL-UP
4.7kW
Figure 28. INA20x Basic Connection
Load
5V Supply
8.3.2 Selecting R_SHUNT
The value chosen for the shunt resistor, R_SHUNT, depends on the application and is a compromise between small-
signal accuracy and maximum permissible voltage loss in the measurement line. High values of R_SHUNT provide
better accuracy at lower currents by minimizing the effects of offset, while low values of R_SHUNT minimize voltage
loss in the supply line. For most applications, best performance is attained with an R_SHUNT value that provides a
full-scale shunt voltage range of 50 mV to 100 mV. Maximum input voltage for accurate measurements is
(V_SHUNT – 0.25) / Gain.
8.3.3 Comparator
The INA203, INA204, and INA205 devices incorporate two open-drain comparators. These comparators typically
have 2 mV of offset and a 1.3-μs (typical) response time. The output of Comparator 1 latches and is reset
through the CMP1 RESET pin, as shown in Figure 30. This configuration applies to both the 10- and 14-pin
versions. Figure 29 illustrates the comparator delay.
The 14-pin versions of the INA203, INA204, and INA205 devices include additional features for comparator
functions. The comparator reference voltage of both Comparator 1 and Comparator 2 can be overridden by
external inputs for increased design flexibility. Comparator 2 has a programmable delay.
8.3.4 Comparator Delay (14-Pin Version Only)
The Comparator 2 programmable delay is controlled by a capacitor connected to the CMP2 Delay Pin; see
Figure 28. The capacitor value (in μF) is selected by using Equation 1:
C_DELAY (in mF) =
t_D
5
(1)
A simplified version of the delay circuit for Comparator 2 is shown in Figure 29. The delay comparator consists of
two comparator stages with the delay between them. I1 and I2 cannot be turned on simultaneously; I1
corresponds to a U1 low output and I2 corresponds to a U1 high output. Using an initial assumption that the U1
output is low, I1 is on, then U2 +IN is zero. If U1 goes high, I2 supplies 120 nA to C_DELAY. The voltage at U2 +IN
begins to ramp toward a 0.6-V threshold. When the voltage crosses this threshold, the U2 output goes high while
the voltage at U2 +IN continues to ramp up to a maximum of 1.2 V when given sufficient time (twice the value of
the delay specified for C_DELAY). This entire sequence is reversed when the comparator outputs go low, so that
returning to low exhibits the same delay.
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