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DLPC200_1 Datasheet, PDF (15/41 Pages) Texas Instruments – DLP® Digital Controller for the DLP5500 DMD
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DLPC200
www.ti.com
DLPS014A – APRIL 2010 – REVISED MAY 2010
TERMINAL FUNCTIONS (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
LED_SUBFRAME
SYNC_0
SYNC_1
SYNC_2
LED_EN
LED_SYNC
LED_SYNCEN
LED_LIT
LED_SENS
LED_SPI_CLK
LED_SPI_CS
LED_SPI_DIR
LED_SPI_MISO
LED_SPI_MOSI
System Interfaces
CFG_CSO
CFG_CLK
CFG_ASDI
CFG_ASDO
CFG_STATUS
CFG_DONE
CFG_MSEL0
CFG_MSEL1
CFG_MSEL2
CFG_MSEL3
CFG_CE
CFG_EN
CFG_CEO
REF_CLK
RESET
PWR_GOOD
RSVD_H10
RSVD_H11
RSVD_H12
RSVD_H6
RSVD_H5
RSVD_H4
RSVD_H2
I/O
NO. TYPE(1)
E26
O3
F26
O3
F25
O3
F24
O3
L28
O3
M21
O3
C24
O3
J28
I3
K27
I3
N26
O3
M26
O3
P25
O3
L27
I3
L26
O3
E2
O3
P3
O3
N7
I3
F4
O3
M6
O3
P24
O3
N22
P23
M22
I3
P22
R8
I3
P4
I3
P28
O1
J27
I3
A14
I3
A23
I3
N4
B2
L2
B2
K4
B2
G1
B2
G5
B2
G6
B2
E1
B2
CLOCK
SYSTEM
Async
Async
Async
Async
Async
Async
Async
Async
Async
Async
LED_SPI_CLK
LED_SPI_CLK
LED_SPI_CLK
LED_SPI_CLK
CFG_DCLK
CFG_DCLK
CFG_DCLK
CFG_DCLK
CFG_DCLK
CFG_DCLK
Async
Async
Async
Async
Async
Async
DESCRIPTION
Subframe signal used by LED Driver. Controlled by programmable
DMD Sequence Timing (Active High)
Extra Strobe. Controlled by programmable DMD Sequence Timing
(Active High)
Extra Strobe. Controlled by programmable DMD Sequence Timing
(Active High)
Extra Strobe. Controlled by programmable DMD Sequence Timing
(Active High)
LED Driver Enable. Active low output control to external LED Drive
Logic.
Reserved for future use; weak pull-up applied
Inverted LED_LIT signal
LED Driver Status
Reserved for future use.
LED SPI MASTER CLOCK
LED SPI MASTER Chip Select
LED SPI MASTER Driver Direction
LED SPI MASTER Data IN
LED SPI MASTER Data OUT; weak pull-up applied
Chip Select Output for an external serial configuration device. Active
low.
Configuration Serial EPROM data clock.
Data input from an external serial configuration device. Provides
configuration data for the device.
Serial Data Output. This pin sends address and control information to
the external PROM during configuration.
Configuration status pin.
Configuration Done status pin. Signal goes high at the end of
configuration.
Configuration Mode Selection signals.
Chip Enable. Active low.
Configuration control. Configuration will start when a low to high
transition is detected at this pin.
50 MHz reference clock, 3.3V
Device reset (active low)
System power good indicator
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DLPC200
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