DAC5672-EP_15 Datasheet, PDF (15/28 Pages) Texas Instruments – DUAL 14-BIT 200-MSPS DIGITAL-TO-ANALOG CONVERTER

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DAC5672-EP
SGLS339A – JUNE 2006 – REVISED OCTOBER 2006
DIGITAL INPUTS AND TIMING (continued)
DA[13:0]/DB[13:0]
WRTA/WRTB
Valid Data
t_su
t_h
t_1ph
CLKA/CLKB
IOUT
or
IOUT
t_pd
t_LAT
Figure 20. Dual-Bus Mode Operation
t_settle
Single-Bus Interleaved Data Interface and Timing
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 21 shows the timing diagram. In
interleaved mode, the A and B channels share the write input (WRTIQ) and update clock (CLKIQ and internal
CLKDACIQ). Multiplexing logic directs the input word at the A-channel input bus to either the A-channel input
latch (SELECTIQ is high) or to the B-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data
value in the B-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ
is low, the data value in the A-channel latch is retained by presenting the latch output data to its input.
In interleaved mode, the A-channel input data rate is twice the update rate of the DAC core. As in dual-bus
mode, it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch
the A- and B-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the A-
and B-DAC latches on the following falling edge of the write inputs. The DAC5672 clock input is divided by a
factor of two before it is presented to the DAC latches.
Correct pairing of the A- and B-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is
divided by two, which would translate to a nondeterministic relation between the rising edges of the CLKIQ and
CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ, with respect
to the data at the input of the DAC latch, is determined. CLKDACIQ is disabled (low) when RESETIQ is high.
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