DAC2932 Datasheet, PDF (15/30 Pages) Burr-Brown (TI) – DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER

DAC2932
www.ti.com
DAC TRANSFER FUNCTION
Each of the I-DACs in the DAC2932 has a complementary
current output, I_OUT1 and I_OUT2. The full-scale output
current, I_OUTFS, is the summation of the two
complementary output currents:
I_OUTFS + I_OUT ) I_OUT
(1)
The individual output currents depend on the DAC code
and can be expressed as:
I_OUT + I_OUTFS (Codeń4096)
(2)
I_OUT + I_OUTFS (4095 * Code)ń4096
(3)
where Code is the decimal representation of the DAC data
input word (0 to 4095).
Additionally, I_OUTFS is a function of the reference current
I_REF, which is determined by the reference voltage and the
external setting resistor, R_SET.
I_OUTFS + 32
I_REF + 32
V_REF
R_SET
(4)
In most cases, the complementary outputs will drive
resistive loads or a terminated transformer. A signal
voltage will develop at each output according to:
V_OUT + I_OUT R_LOAD
(5)
V_OUT + I_OUT R_LOAD
(6)
The value of the load resistance is limited by the output
compliance specification of the DAC2932. To maintain
optimum linearity performance, the compliance voltage at
I_OUT and I_OUT should be limited to +0.5V or less.
SBAS279D − AUGUST 2003 − REVISED JULY 2005
The two single-ended output voltages can be combined to
find the total differential output swing:
V_OUTDIFF + V_OUT * V_OUT
+ ⁽²
Code * 4095)
4096
I _OUTFS
(7)
R_LOAD
POWER-DOWN MODES
The DAC2932 has several modes of operation. Besides
normal operation, the I-DAC section features a Standby
mode and a full power-down mode, while the V-DAC
section has one power-down mode. All modes are
controlled by appropriate logic levels on the assigned pins
of the DAC2932. Table 1 lists all pins and possible modes.
The pins have internal pull-ups or pull-downs; if left open,
all pins will resume logic levels that place the I-DAC and
V-DAC in a normal operating mode (fully functional).
When in Standby mode the analog functions of the I-DAC
section are powered down. The internal logic is still active
and will consume some power if the clock remains applied.
To further reduce the power in Standby mode the CS pin
may be pulled high, which disables the internal logic from
being clocked, even with the clock signal applied.
If CS remains low during the Standby mode and a running
clock remains applied, any new data on the parallel data
port will be latched into the DAC. The analog output,
however, will not be updated as long as the I-DACs remain
in Standby mode.
Table 1. Power-Down Modes
PD (16) STBY(17) CS (18) PDV (44)
0
0
0
X
0
0
1
X
0
1
0
X
DAC
I-DAC enabled
I-DAC disabled
I-DAC enabled
MODE
Standby; data can still be written into the DACs
with running clock applied
Standby; writing into DAC disabled—clock input
disabled by CS
Normal operation (return from Standby)
0
1
1
1
X
X
0
X
X
X
X
X
NOTE: X = don’t care.
X
I-DAC disabled Data input and clock input disabled; use when
multiple devices on one bus
X
I-DAC disabled Full power-down; STBY and CS have no effect
0
V-DAC enabled V-DAC normal operation
1
V-DAC disabled V-DAC in power-down mode; independent
operation of any I-DAC power-down
configuration
DAC OUTPUTS
High-Z
High-Z
Last state prior to
Standby
Last data held
High-Z
All outputs; High-Z
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