CDCL6010 Datasheet, PDF (15/24 Pages) Texas Instruments – 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer

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Divide
Ratio
1
2
4
5
8
10
16
20
32
40
80
SELP1[3] or
SELP0[3]
0
0
0
0
0
0
0
0
1
1
1
CDCL6010
SLLS780 – FEBRUARY 2007
Table 1. Divide Ratio Settings for Post-Divider P0 or P1
SELP1[2] or
SELP0[2]
0
0
0
0
1
1
1
1
0
0
0
SELP1[1] or
SELP0[1]
0
0
1
1
0
0
1
1
0
0
1
SELP1[0] or
SELP0[0]
0
1
0
1
0
1
0
1
0
1
0
Notes
Default
Divide
Ratio
32
40
SELN[3]
1
1
Table 2. Divide Ratio Settings for Divider N
SELN[2]
0
0
SELN[1]
0
0
SELN[0]
0
1
Notes
Default
Divide
Ratio
1
2
4
8
SELM[1]
0
0
1
1
Table 3. Divide Ratio Settings for Divider M
SELM[0]
0
1
0
1
Notes
Default
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