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| AFE5805 Datasheet, PDF (15/32 Pages) Texas Instruments – 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND | |||
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AFE5805
www.ti.com
SBOS421A â MARCH 2008 â REVISED MARCH 2008
SERIAL REGISTER MAP
Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1)(2)(3)(4)
ADDRESS
IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
DESCRIPTION
DEFAULT
00
X
S_RST
Self-clearing software RESET.
Inactive
RE
03
0
0
0
0
0
0
0
0
0
0
S_
VC
0
0
0
0
0
A
16
X
X
X
X
X
X X X X X X X X X 1 1 VCA_DATA<0:15>
17
X
X
X
X
X
X X X X X X X X X X X VCA_DATA<16:317
18
X X X X X X X X VCA_DATA<32:39>
XXXX
PDN_CH<1:4>
Channel-specific ADC
power-down mode.
Inactive
x
XXXX
PDN_CH<1:5>
Channel-specific ADC
power-down mode.
Inactive
0F
X
PDN_PARTIAL
Partial power-down mode (fast
recovery from power-down).
Inactive
0X
PDN_COMPLETE
Register mode for complete
power-down (slower recovery).
Inactive
X0
PDN_PIN_CFG
Configures the PD pin for partial Complete
power-down mode.
power-down
11
X
X XX
XXX
LVDS current drive
X X X ILVDS_LCLK<2:0> programmability for LCLKN and
LCLKP pins.
3.5mA drive
ILVDS_FRAME
<2:0>
LVDS current drive
programmability for ADCLKN and 3.5mA drive
ADCLKP pins.
ILVDS_DAT<2:0>
LVDS current drive
programmability for OUTN and
OUTP pins.
3.5mA drive
EN_LVDS_TERM
Enables internal termination for
LVDS buffers.
Termination
disabled
1
12
1
1
14
x
X XX
X
X
X
TERM_LCLK<2:0>
Programmable termination for
LCLKN and LCLKP buffers.
Termination
disabled
XXX
TERM_FRAME
<2:0>
Programmable termination for
ADCLKN and ADCLKP buffers.
Termination
disabled
TERM_DAT<2:0>
Programmable termination for
OUTN and OUTP buffers.
Termination
disabled
XXXX
LFNS_CH<8:1>
Channel-specific, low-frequency
noise suppression mode enable.
Inactive
XXXX
LFNS_CH<8:5>
Channel-specific, low-frequency
noise suppression mode enable.
Inactive
24
x
X
X
X
X
X
X
X
X
INVERT_CH<1:4>
Swaps the polarity of the analog
input pins electrically.
INVERT_CH<8:5>
Swaps the polarity of the analog
input pins electrically.
INP is
positive
input
INP is
positive
input
X00
EN_RAMP
Enables a repeating full-scale
ramp pattern on the outputs.
Inactive
0X0
DUALCUSTOM_
PAT
Enables the mode wherein the
output toggles between two
defined codes.
Inactive
25
00X
SINGLE_CUSTOM
_PAT
Enables the mode wherein the
output is a constant specified
code.
Inactive
XX
BITS_CUSTOM1
<11:10>
2MSBs for a single custom
pattern (and for the first code of
the dual custom pattern). <11> is
the MSB.
Inactive
XX
BITS_CUSTOM2 2MSBs for the second code of
<11:10>
the dual custom pattern.
Inactive
26
X
X
X
X
X
X XXXX
BITS_CUSTOM1
<9:0>
10 lower bits for the single
custom pattern (and for the first
code of the dual custom pattern).
<0> is the LSB.
Inactive
(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.
(2) X = Register bit referenced by the corresponding name and description (default is 0).
(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.
(4) Multiple functions in a register should be programmed in a single write operation.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): AFE5805
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